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dc.contributor.author莊立溥en_US
dc.contributor.author張銘宏en_US
dc.contributor.author黃威en_US
dc.date.accessioned2014-12-16T06:16:33Z-
dc.date.available2014-12-16T06:16:33Z-
dc.date.issued2012-11-11en_US
dc.identifier.govdocH03L007/08zh_TW
dc.identifier.govdocH03L007/16zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105953-
dc.description.abstract本發明揭露了一種全數位自我校正多相位延遲鎖定迴路,其包含四個主要的區塊,分別為:一組數位式控制延遲線,一相位偵測器,一鎖定單元,及一自我校正單元。數位式控制延遲線係由K個相同之延遲級(delay stage)串連所形成,而所有的延遲級皆係由兩組控制訊號C[M:0]與Bi[N:0]所控制。C[M:0]係由採用非平衡式二元搜尋演算法之鎖定單元所產生。當延遲鎖定迴路鎖定時,自我校正單元將產生Bi[N:0]訊號以調整各級輸出訊號之間的相位差。zh_TW
dc.language.isozh_TWen_US
dc.title全數位快速鎖定自我校正多相位延遲鎖定迴路zh_TW
dc.typePatentsen_US
dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumberI376879zh_TW
Appears in Collections:Patents


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