| 標題: | 以實證觀點檢視我國積體電路電路布局保護法十二年的運作 |
| 作者: | 張添榜 Chang, Tien-pang 科技法律研究所 Institute of Technology Law |
| 關鍵字: | 積電電路;電路布局;晶片;積體電路電路布局保護法;晶片保護法;實證研究;實證分析;Integrated circuit;Circuit layout;Chip;Integrated circuits layout protection law;Chip protection act;Empirical study;Empirical analysis |
| 公開日期: | 2009 |
| URI: | http://hdl.handle.net/11536/107654 http://www.itl.nctu.edu.tw/tlr_n/ch/list6_1.html |
| ISSN: | 1811-3095 |
| 期刊: | 科技法學評論 |
| Volume: | 6 |
| Issue: | 1 |
| 起始頁: | 75 |
| 結束頁: | 111 |
| Appears in Collections: | Technology Law Review |
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- Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits / Lin, Chun-Yu;Ker, Ming-Dou
- 考量軟性電子錯誤率之電路布局強化 / 劉宜武;溫宏斌;Liu, Yi-Wu;Wen, Hung-Pin
- ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration / Ker, MD;Chuang, CH
- ESD (Electrostatic Discharge) protection design for nanoelectronics in CMOS technology / Ker, Ming-Dou
- Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process / Ker, Ming-Dou;Lin, Chun-Yu;Chang, Tang-Long
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