Parallel pixel processing using programmable gate arrays

標題:	Parallel pixel processing using programmable gate arrays
作者:	Budgett, DM Tang, PE Sharp, JH Chatwin, CR Young, RCD Wang, RK Scott, BF 電控工程研究所 Institute of Electrical and Control Engineering
關鍵字:	programmable logic devices;image processing;parallel algorithms
公開日期:	15-八月-1996
摘要:	A reconfigurable hardware design permits very fast feature extraction from high frame rate video images. By implementing parallel pixel processing paths in programmable gate arrays, a wide range of image processing algorithms can be implemented in realtime.
URI:	http://hdl.handle.net/11536/1105
ISSN:	0013-5194
期刊:	ELECTRONICS LETTERS
Volume:	32
Issue:	17
起始頁:	1557
結束頁:	1559
顯示於類別：	期刊論文

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