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dc.contributor.authorLo, Wen-Chengen_US
dc.contributor.authorWu, Shien-Yangen_US
dc.contributor.authorChang, Sun-Jayen_US
dc.contributor.authorChiang, Mu-Chien_US
dc.contributor.authorLin, Chih-Yungen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.date.accessioned2014-12-08T15:14:32Z-
dc.date.available2014-12-08T15:14:32Z-
dc.date.issued2007-03-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.46.1124en_US
dc.identifier.urihttp://hdl.handle.net/11536/11053-
dc.description.abstractIn this study, we compared the effects of negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) on the core and input/output (I/O) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) fabricated using the different gate dielectrics of plasma nitrided oxide (PNO) and thermally nitrided oxide (TNO). The mobility and constant overdrive current of the PMOSFETs fabricated using PNO as a gate oxide material are about 30 and 23% higher than those of the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide bulk trap density but a better NBTI than the devices fabricated using TNO at a normal stressed bias due to a low interface trap density.en_US
dc.language.isoen_USen_US
dc.subjectNBTIen_US
dc.subjectHCIen_US
dc.subjectPNOen_US
dc.subjectTNOen_US
dc.subjectcoreen_US
dc.subjectI/Oen_US
dc.titleSystematical study of reliability issues in plasma-nitrided and thermally nitrided oxides for advanced dual-gate oxide p-channel metal-oxide-semiconductor field-effect transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.46.1124en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERSen_US
dc.citation.volume46en_US
dc.citation.issue3Aen_US
dc.citation.spage1124en_US
dc.citation.epage1128en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000245192100051-
dc.citation.woscount2-
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