先進金氧半場效電晶體閘極工程對改善元件特性及可靠度之研究

Abstract

在本論文中，我們針對先進元件的閘極工程整合部分對特性及可靠度的改善進行研究，涵蓋的內容包括淺溝渠隔離(STI)所造成的區域性單向壓縮應力在<110>及<100>通道方向的比較；在(111)晶向基版上利用氮化矽覆蓋層來改善N型金氧半場效電晶體的特性；以電漿氮化氧化層或熱氮化氧化層使用在雙閘極氧化層厚度的P型金氧半場效電晶體上在負電壓溫度不穩定性及熱載子注入等可靠度之比較，以及元件使用以鉿為基本材料之高介電係數介電層在正電壓溫度不穩定性分析中捕捉/反捕捉電子的可靠度分析。 我們完整地研究了65奈米技術的P型金氧半場效電晶體在<110>及<100>通道方向上對主動區佈局的相依性以及淺溝渠隔離所造成的單向壓縮應力對其特性的影響。對65奈米的P型金氧半場效電晶體而言，當源/汲極長度從0.21微米增加到10微米，<100>通道方向在飽和汲極電流特性方面會比<110>通道的元件高出約從8 % 提高到15 ％。再者，我們也證明了對於不管在通道長度或寬度方向來說，<100>通道的元件對硼的擴散有較高的抑制能力以及對淺溝渠隔離所造成的應力也有較低的感受度。 我們亦利用高應力之氮化矽覆蓋層以及非晶矽與多晶矽堆疊之閘極結構等區域應變通道技術在(111)晶向矽基版上製作出N型金氧半場效電晶體。當氧化矽覆蓋層或非晶矽層厚度增加時，元件的飽和電流及轉移電導也隨之上升。我們的實驗結果顯示相對於非晶矽厚度為20奈米的元件而言，非晶矽厚度為70奈米的元件在飽和電流方面有約6.7 %的改善；在轉移電導方面則有約10.2 %的增加。 此外，我們比較了使用電漿氮化氧化層及熱氮化氧化層兩種不同閘極介電層的核心與輸入/輸出之P型金氧半場效電晶體受到負電壓溫度不穩定性及熱載子注入等可靠度的影響。以電漿氮化氧化層作為閘極氧化層材料之P型金氧半場效電晶體在漂移率方面比熱氮化氧化層元件高了約30 %，定電壓過驅動電流的值也比熱氮化氧化層高了約23 %。相較於熱氮化氧化層，電漿氮化氧化層之核心P型金氧半場效電晶體因為在氧化層與矽基版界面有較低之氮的濃度，所以有較佳的負電壓溫度不穩定性及熱載子注入抵抗能力。然而，電漿氮化氧化層之輸入/輸出P型金氧半場效電晶體則表現出較高的熱載子注入造成的特性退化率因為其有較高的氧化層內的主體缺陷。不過對於操作在一般電壓之負電壓溫度不穩定性方面，仍是優於熱氮化氧化層歸因於較低的界面缺陷密度。 最後，我們論證了以二氧化鉿(HfO2)及鉿之氮氧化矽(HfSiON)兩種材料作為閘極氧化層的N型金氧半場效電晶體在正電壓溫度不穩定性可靠度的特性退化。對以鉿為基本材料之高介電係數介電層而言，在正電壓溫度不穩定性可靠度測試期間所產生的氧化層主體缺陷會主導元件的正電壓溫度不穩定性之特性退化。在正電壓溫度不穩定性可靠度測試中，較低的臨界啟始電壓退化以及氧化層主體缺陷產生率，證明了鉿之氮氧化矽的薄膜品質優於二氧化鉿。此外，在正電壓溫度不穩定性可靠度測試期間，相對於二氧化鉿介電層而言，鉿之氮氧化矽則有較淺的電荷捕捉能階。

In this dissertation, we investigated the gate engineering integration for advanced device performance and reliability improvement including the comparison of STI-induced local uniaxial compressive stress in <110>- and <100>-channel directions, the use of SiN capping layer on (111) orientation substrate to improve the NMOSFET performance, the reliability comparisons in negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) between dual gate oxide PMOSFETs using plasma nitrided oxide (PNO) and thermally nitrided oxide (TNO) and the positive-bias temperature instability (PBTI) trapping/de-trapping reliability issues for devices using Hf-based high-k dielectrics. Active-region layout dependence and STI-induced uniaxial compressive stress impact on the performance of 65 nm technology PMOSFETs with <110>- and <100>-channel directions were fully investigated. For 65 nm PMOSFET, <100>-channel show as higher as about 8 ~ 15% in Id_sat than <110>-channel devices as S/D length increased from 0.21 □m to 10 □m. Furthermore, higher immunity to boron diffusion and less sensitivity on STI-induced strain in both of channel length and width directions for <100>-channel devices were also demonstrated. We also investigated NMOSEFT fabricated with local strained channel techniques on a (111) Si substrate using a SiN capping layer with high mechanical stress and the stack gate of amorphous silicon (□-Si) and polycrystalline silicon (poly-Si). The on-current and transconductance (Gm) increased with increasing SiN capping layer or □-Si layer thickness. Our experimental results show that devices with a 700 Å □-Si layer show a 6.7% on-current improvement percentage relative to those with a 200 Å □-Si layer, and a corresponding Gm improvement percentage of 10.2%. Besides, we compared the effects of NBTI and HCI on the core and input/output (I/O) PMOSFET fabricated using the different gate dielectrics of PNO and TNO. The mobility and constant overdrive current of the PMOSFETs fabricated using PNO as a gate oxide material are about 30% and 23% higher than those of the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide bulk trap density but a better NBTI than the devices fabricated using TNO at a normal stressed bias due to a low interface trap density. In the final part, PBTI degradation for HfO2 and HfSiON NMOSFETs with the metal gate electrode has been successfully demonstrated. The generated oxide trap during PBTI stress will dominate the PBTI characteristics for Hf-based gate dielectrics. The reduction of threshold voltage degradation and oxide trap generation under PBTI stress indicates that the HfSiON thin film quality is better than HfO2. In addition, as compared to HfO2 dielectrics, the HfSiON has shallower charge trapping level under PBTI stress.