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dc.contributor.authorLee, Ming-Hsienen_US
dc.contributor.authorChang, Kai-Hsiangen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.date.accessioned2014-12-08T15:14:39Z-
dc.date.available2014-12-08T15:14:39Z-
dc.date.issued2007-03-01en_US
dc.identifier.issn0021-8979en_US
dc.identifier.urihttp://dx.doi.org/10.1063/1.2710302en_US
dc.identifier.urihttp://hdl.handle.net/11536/11106-
dc.description.abstractA test structure was proposed to investigate the spatial and temporal evolution of hot-carrier degradation in n-channel poly-Si thin-film transistors. Our experimental results clearly show that the initial damage during the early stage of hot-carrier stressing, which is still undetectable by conventional test structures, can be easily observed by the structure. In addition, the proposed test structure is also capable of resolving the evolution of the degradation along the channel, thus providing a powerful tool to study the location-dependent damage mechanisms. (c) 2007 American Institute of Physics.en_US
dc.language.isoen_USen_US
dc.titleSpatially and temporally resolving the degradation of n-channel poly-Si thin-film transistors under hot-carrier stressingen_US
dc.typeArticleen_US
dc.identifier.doi10.1063/1.2710302en_US
dc.identifier.journalJOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume101en_US
dc.citation.issue5en_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000244945400158-
dc.citation.woscount4-
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