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dc.contributor.authorChen, Iian-Longen_US
dc.contributor.authorLin, Yu-Kunen_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.date.accessioned2014-12-08T15:14:42Z-
dc.date.available2014-12-08T15:14:42Z-
dc.date.issued2007en_US
dc.identifier.issn1520-6149en_US
dc.identifier.urihttp://hdl.handle.net/11536/11135-
dc.description.abstractThis paper presents a fast and low cost context adaptive binary arithmetic encoder for H.264/MPEG-4 AVC video coding standard through both algorithm level and architecture level optimizations. First in the algorithm level, we process the binarization and context generation in parallel to reduce the encoding iteration cycles to three or four cycles from five cycles in the previous design. Second, in the architecture level, we reduce the cycles of renormalization loops by employing one-skipping and bit-parallelism, and save hardware cost of arithmetic coder by merging three different modes. The implemented design shows that it can achieve the 333MHz frequency with only 13.3K gate count.en_US
dc.language.isoen_USen_US
dc.subjectCABACen_US
dc.subjectH.264en_US
dc.titleLow cost context adaptive arithmetic coder for H.264/MPEG-4 AVC video codingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol II, Pts 1-3en_US
dc.citation.spage105en_US
dc.citation.epage108en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000248908100027-
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