完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tai, Ya-Hsiang | en_US |
dc.contributor.author | Huang, Shih-Che | en_US |
dc.contributor.author | Lin, Chien Wen | en_US |
dc.contributor.author | Chiu, Hao Lin | en_US |
dc.date.accessioned | 2014-12-08T15:15:06Z | - |
dc.date.available | 2014-12-08T15:15:06Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.issn | 0013-4651 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/11335 | - |
dc.identifier.uri | http://dx.doi.org/10.1149/1.2735921 | en_US |
dc.description.abstract | In this paper, the degradation of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dc stress is investigated with measurement of the capacitance between the source and the gate (C-GS), as well as the capacitance between the drain and the gate (C-GD). It is discovered that the degradation in C-GD curves of the device after hot carrier stress shows apparent frequency dependence, while that in the C-GS curves remains almost the same. A circuit model based on the channel resistance extracted from the current-voltage behavior is proposed to describe the frequency dependence of the capacitance behavior. From this model, it is revealed that the anomalous frequency-dependent capacitance-voltage characteristics may simply reflect the transient behaviors of the channel resistances. Besides, it was found that the C-GS curves after self-heating effect exhibit a significant shift in the positive direction and an additional increase for the smaller gate voltage, while the C-GD curves show only positive shifts. By employing simulation, it was proved that the self-heating effect creates interface states near the source region and increases the deep states in the poly-Si film near drain. The proposed circuit model further explains the behavior of the C-GS and C-GD curves for the stressed device at different measuring frequencies. (C) 2007 The Electrochemical Society. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/1.2735921 | en_US |
dc.identifier.journal | JOURNAL OF THE ELECTROCHEMICAL SOCIETY | en_US |
dc.citation.volume | 154 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | H611 | en_US |
dc.citation.epage | H618 | en_US |
dc.contributor.department | 光電工程學系 | zh_TW |
dc.contributor.department | 顯示科技研究所 | zh_TW |
dc.contributor.department | Department of Photonics | en_US |
dc.contributor.department | Institute of Display | en_US |
dc.identifier.wosnumber | WOS:000246892000062 | - |
dc.citation.woscount | 22 | - |
顯示於類別: | 期刊論文 |