標題: | A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard |
作者: | Hung, Jui-Hui Chen, Sau-Gee 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | LDPC code;decoder;architecture |
公開日期: | 2007 |
摘要: | In this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.18 mu m process technology. |
URI: | http://hdl.handle.net/11536/11512 |
ISBN: | 978-1-4244-1834-3 |
期刊: | 2007 IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY, VOLS 1-3 |
起始頁: | 219 |
結束頁: | 224 |
顯示於類別: | 會議論文 |