完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Li, Katherine Shu-Min | en_US |
dc.contributor.author | Su, Chauchin | en_US |
dc.contributor.author | Chang, Yao-Wen | en_US |
dc.contributor.author | Lee, Chung-Len | en_US |
dc.contributor.author | Chen, Jwu E. | en_US |
dc.date.accessioned | 2014-12-08T15:15:31Z | - |
dc.date.available | 2014-12-08T15:15:31Z | - |
dc.date.issued | 2006-11-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCAD.2006.881330 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/11606 | - |
dc.description.abstract | An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | crosstalk fault | en_US |
dc.subject | delay fault | en_US |
dc.subject | fault diagnosis | en_US |
dc.subject | interconnections | en_US |
dc.subject | oscillation ring (OR) test scheme | en_US |
dc.title | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCAD.2006.881330 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 25 | en_US |
dc.citation.issue | 11 | en_US |
dc.citation.spage | 2513 | en_US |
dc.citation.epage | 2525 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000241567000018 | - |
dc.citation.woscount | 6 | - |
顯示於類別: | 期刊論文 |