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dc.contributor.authorLi, Katherine Shu-Minen_US
dc.contributor.authorSu, Chauchinen_US
dc.contributor.authorChang, Yao-Wenen_US
dc.contributor.authorLee, Chung-Lenen_US
dc.contributor.authorChen, Jwu E.en_US
dc.date.accessioned2014-12-08T15:15:31Z-
dc.date.available2014-12-08T15:15:31Z-
dc.date.issued2006-11-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2006.881330en_US
dc.identifier.urihttp://hdl.handle.net/11536/11606-
dc.description.abstractAn interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution.en_US
dc.language.isoen_USen_US
dc.subjectcrosstalk faulten_US
dc.subjectdelay faulten_US
dc.subjectfault diagnosisen_US
dc.subjectinterconnectionsen_US
dc.subjectoscillation ring (OR) test schemeen_US
dc.titleIEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faultsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2006.881330en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume25en_US
dc.citation.issue11en_US
dc.citation.spage2513en_US
dc.citation.epage2525en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000241567000018-
dc.citation.woscount6-
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