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dc.contributor.authorTseng, Wenliangen_US
dc.contributor.authorLiu, Chien-Nan Jimmyen_US
dc.contributor.authorSu, Chauchinen_US
dc.date.accessioned2014-12-08T15:15:32Z-
dc.date.available2014-12-08T15:15:32Z-
dc.date.issued2006-11-01en_US
dc.identifier.issn0916-8524en_US
dc.identifier.urihttp://dx.doi.org/10.1093/ietele/e89-c.11.1713en_US
dc.identifier.urihttp://hdl.handle.net/11536/11625-
dc.description.abstractThis paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.en_US
dc.language.isoen_USen_US
dc.subjectmodel-order reductionen_US
dc.subjectpassive macromodelsen_US
dc.subjectstate-space time-delays systemsen_US
dc.subjecttransmission linesen_US
dc.titlePassive reduced-order macro-modeling for linear time-delay interconnect systemsen_US
dc.typeArticleen_US
dc.identifier.doi10.1093/ietele/e89-c.11.1713en_US
dc.identifier.journalIEICE TRANSACTIONS ON ELECTRONICSen_US
dc.citation.volumeE89Cen_US
dc.citation.issue11en_US
dc.citation.spage1713en_US
dc.citation.epage1718en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000242506600034-
dc.citation.woscount0-
Appears in Collections:Articles