Passive reduced-order macro-modeling for linear time-delay interconnect systems

doi:10.1093/ietele/e89-c.11.1713

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tseng, Wenliang	en_US
dc.contributor.author	Liu, Chien-Nan Jimmy	en_US
dc.contributor.author	Su, Chauchin	en_US
dc.date.accessioned	2014-12-08T15:15:32Z	-
dc.date.available	2014-12-08T15:15:32Z	-
dc.date.issued	2006-11-01	en_US
dc.identifier.issn	0916-8524	en_US
dc.identifier.uri	http://dx.doi.org/10.1093/ietele/e89-c.11.1713	en_US
dc.identifier.uri	http://hdl.handle.net/11536/11625	-
dc.description.abstract	This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.	en_US
dc.language.iso	en_US	en_US
dc.subject	model-order reduction	en_US
dc.subject	passive macromodels	en_US
dc.subject	state-space time-delays systems	en_US
dc.subject	transmission lines	en_US
dc.title	Passive reduced-order macro-modeling for linear time-delay interconnect systems	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1093/ietele/e89-c.11.1713	en_US
dc.identifier.journal	IEICE TRANSACTIONS ON ELECTRONICS	en_US
dc.citation.volume	E89C	en_US
dc.citation.issue	11	en_US
dc.citation.spage	1713	en_US
dc.citation.epage	1718	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:000242506600034	-
dc.citation.woscount	0	-
顯示於類別：	期刊論文