標題: RLC coupling-aware simulation and on-chip bus encoding for delay reduction
作者: Tu, Shang-Wei
Chang, Yao-Wen
Jou, Jing-Yang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: bus-invert method;coupling;inductance;interconnect delay;worst case switching pattern
公開日期: 1-十月-2006
摘要: This paper shows. that the worst case switching pattern that incurs the longest bus delay While considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses.
URI: http://dx.doi.org/10.1109/TCAD.2005.860956
http://hdl.handle.net/11536/11726
ISSN: 0278-0070
DOI: 10.1109/TCAD.2005.860956
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 25
Issue: 10
起始頁: 2258
結束頁: 2264
顯示於類別:期刊論文


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