Title: RLC coupling-aware simulation and on-chip bus encoding for delay reduction
Authors: Tu, Shang-Wei
Chang, Yao-Wen
Jou, Jing-Yang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: bus-invert method;coupling;inductance;interconnect delay;worst case switching pattern
Issue Date: 1-Oct-2006
Abstract: This paper shows. that the worst case switching pattern that incurs the longest bus delay While considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses.
URI: http://dx.doi.org/10.1109/TCAD.2005.860956
http://hdl.handle.net/11536/11726
ISSN: 0278-0070
DOI: 10.1109/TCAD.2005.860956
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 25
Issue: 10
Begin Page: 2258
End Page: 2264
Appears in Collections:Articles


Files in This Item:

  1. 000240926700030.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.