標題: | RLC effects on worst-case switching pattern for on-chip buses |
作者: | Tu, SW Jou, JY Chang, YW 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2004 |
摘要: | Inductance effects on on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially on global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we show that the worst-case switching patterns that incur the largest bus delay are completely different while considering RC and RLC effects. The finding implies that existing encoding schemes based on RC model might not improve or even worsen the bus delay when inductance effects become dominant. |
URI: | http://hdl.handle.net/11536/18403 |
期刊: | 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS |
起始頁: | 945 |
結束頁: | 948 |
顯示於類別: | 會議論文 |