標題: | Fast packet classification using bit compression with fast boolean expansion |
作者: | Chen, Chien Hsu, Chia-Jen Huang, Chi-Chia 資訊工程學系 Department of Computer Science |
關鍵字: | router;packet classification;bitmap intersection;bit compression;Boolean expansion;network processor |
公開日期: | 1-一月-2008 |
摘要: | To support applications such as Internet security, virtual private networks, and Quality of Service (QoS), Internet routers need to quickly classify incoming packets into flows. Packet classification uses information contained in the packet header and a predefined rule table in the routers. In general, packet classification on multiple fields is a difficult problem. Hence, researchers have proposed a variety of classification algorithms. This paper presents a novel packet classification algorithm, the bit compression algorithm. As with the best-known classification algorithm, bitmap intersection, bit compression is based on the multiple dimensional range lookup approach. Since bit vectors of the bitmap intersection contain many "0" bits, the bit vectors could be compressed. We compress the bit vectors by preserving only useful information and removing the redundant bits of the bit vectors. An additional index table would be created to keep track of the rule number associated with the remaining bits. Additionally, the wildcard rules enable an extensive improvement in the storage requirement. A novel Fast Boolean Expansion enables our scheme to obtain better classification speed even under a large number of wildcard rules. Compared to the bitmap intersection algorithm, the bit compression algorithm reduces the storage complexity in the average case from O(dN(2)) (for bitmap intersection) to theta(dN.log N), where d denotes the number of dimensions and N represents the number of rules. The proposed scheme cuts the cost of packet classification engine and increases classification performance by accessing less memory, which is the performance bottleneck in the packet classification engine implementation using a network processor. |
URI: | http://hdl.handle.net/11536/119 |
ISSN: | 1016-2364 |
期刊: | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING |
Volume: | 24 |
Issue: | 1 |
起始頁: | 61 |
結束頁: | 81 |
顯示於類別: | 會議論文 |