完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Chih-Hsien | en_US |
dc.contributor.author | Chen, Chih-Ning | en_US |
dc.contributor.author | Wang, You-Jiun | en_US |
dc.contributor.author | Hsiao, Ju-Yuan | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.date.accessioned | 2014-12-08T15:16:13Z | - |
dc.date.available | 2014-12-08T15:16:13Z | - |
dc.date.issued | 2006-07-01 | en_US |
dc.identifier.issn | 1057-7130 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSII.2006.875316 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/12050 | - |
dc.description.abstract | In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scrambler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-mu m CMOS process. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | parallel scrambler | en_US |
dc.subject | register | en_US |
dc.subject | XOR | en_US |
dc.title | Parallel scrambler for high-speed applications | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSII.2006.875316 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | en_US |
dc.citation.volume | 53 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | 558 | en_US |
dc.citation.epage | 562 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000239263900010 | - |
dc.citation.woscount | 5 | - |
顯示於類別: | 期刊論文 |