完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, HC | en_US |
dc.contributor.author | Lee, MH | en_US |
dc.contributor.author | Chang, KH | en_US |
dc.date.accessioned | 2014-12-08T15:16:20Z | - |
dc.date.available | 2014-12-08T15:16:20Z | - |
dc.date.issued | 2006-07-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2006.876314 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/12113 | - |
dc.description.abstract | A novel thin-film transistor test structure is proposed for monitoring the device hot-carrier (HQ degradations. The new test structure consists of several source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. This unique feature allows, for the first time, the study of spatial resolution of HC degradations along the channel of the test transistor after stressing. The extent of degradation as well as the major degradation mechanisms along the channel of the test transistor can be clearly identified. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | grain boundary | en_US |
dc.subject | hot-carrier (HC) effects | en_US |
dc.subject | poly-Si | en_US |
dc.subject | test structure | en_US |
dc.subject | thin-film transistor (TFT) | en_US |
dc.title | Spatially resolving the hot carrier degradations of poly-Si thin-film transistors using a novel test structure | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2006.876314 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 27 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | 561 | en_US |
dc.citation.epage | 563 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000238712200011 | - |
dc.citation.woscount | 7 | - |
顯示於類別: | 期刊論文 |