Polymer space-charge-limited transistor

doi:10.1063/1.2207838

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chao, YC	en_US
dc.contributor.author	Meng, HF	en_US
dc.contributor.author	Horng, SF	en_US
dc.date.accessioned	2014-12-08T15:16:34Z	-
dc.date.available	2014-12-08T15:16:34Z	-
dc.date.issued	2006-05-29	en_US
dc.identifier.issn	0003-6951	en_US
dc.identifier.uri	http://dx.doi.org/10.1063/1.2207838	en_US
dc.identifier.uri	http://hdl.handle.net/11536/12237	-
dc.description.abstract	A metal grid is sandwiched between poly(3-hexylthiophene) to form a solid-state version of vacuum tube triode, where the vertical space-charge-limited current is modulated by the grid potential. The Al grid contains random submicron openings formed by a nonlithographic method. The multilayer polymer structure is made by spin coating. The operating voltage of the polymer space-charge-limited transistor is 3 V, and the current gain of 506 is obtained. The characteristics of the transistor can be tuned by the diameters and the density of the openings on the grid. Similar to the vacuum tube triode, the current follows a power law voltage dependence.	en_US
dc.language.iso	en_US	en_US
dc.title	Polymer space-charge-limited transistor	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1063/1.2207838	en_US
dc.identifier.journal	APPLIED PHYSICS LETTERS	en_US
dc.citation.volume	88	en_US
dc.citation.issue	22	en_US
dc.citation.epage		en_US
dc.contributor.department	物理研究所	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Institute of Physics	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000238001900090	-
dc.citation.woscount	34	-
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