Design and implementation of reconfigurable RSA cryptosystem

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, Yun-Lu	en_US
dc.contributor.author	Tseng, Chih-Yeh	en_US
dc.contributor.author	Chang, Hsie-Chia	en_US
dc.date.accessioned	2014-12-08T15:16:35Z	-
dc.date.available	2014-12-08T15:16:35Z	-
dc.date.issued	2007	en_US
dc.identifier.isbn	978-1-4244-0582-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/12246	-
dc.description.abstract	In this paper, the hardware implementation of a reconfigurable RSA cryptosystern is presented. In order to match distinct security levels, the modified Montgomery modular multiplication algorithm is introduced into this 512/1024/2048/40196bits RSA encryption/decryption. The huge number of register is also replaced by 5 memory blocks. As a result, our design including 5 memory blocks achieves the baud rate of 99kb/s for 512-bit, 29kb1s for 1024-bit, 6.8kslb for 2048-bit and 1.7kb/s for 4096-bit on Xilinx Vertex2 XC2V8000 of 6783 slices.	en_US
dc.language.iso	en_US	en_US
dc.title	Design and implementation of reconfigurable RSA cryptosystem	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers	en_US
dc.citation.spage	252	en_US
dc.citation.epage	255	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000247000000063	-
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