標題: The IC design of a high speed RSA processor
作者: Yang, CC
Jen, CW
Chang, TS
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電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
公開日期: 1996
摘要: In this paper, we proposed a new algorithm based on Montgomery's algorithm[1] to calculate modular multiplication that is the core arithmetic operation in RSA cryptosystem. Since the critical path delay in modular multiplication operation is reduced the new design yields a very fast implementation. We have implemented a 512-bit single chip RSA processor based on our modified algorithm with Compass 0.6 mu n SPDM cell library. By our modified modular exponentiation algorithm if takes about 1.5n(2) clock cycles to finish one n-bit RSA modular exponentiation operation in our architecture. The simulation results show that we can operate up to 125Mhz, therefore the baud rate of our 512-bit RSA processor is about 164k bits/sec.
URI: http://hdl.handle.net/11536/19887
ISBN: 0-7803-3702-6
期刊: APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96
起始頁: 33
結束頁: 36
顯示於類別:會議論文