Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, Chia-Pin	en_US
dc.contributor.author	Tsui, Bing-Yue	en_US
dc.contributor.author	Hsieh, Chih-Ming	en_US
dc.contributor.author	Huang, Chih-Feng	en_US
dc.date.accessioned	2014-12-08T15:16:48Z	-
dc.date.available	2014-12-08T15:16:48Z	-
dc.date.issued	2007	en_US
dc.identifier.isbn	978-1-4244-0584-8	en_US
dc.identifier.uri	http://hdl.handle.net/11536/12357	-
dc.description.abstract	Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction were fabricated. Symmetric threshold voltage was obtained by implant-to-silicide technique. Lateral growth rate and thermal stability of NiSi on SiO2 were investigated. Single silicide and low temperature process make the proposed process very promising in sub-45nm technology nodes.	en_US
dc.language.iso	en_US	en_US
dc.title	Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Proceedings of Technical Papers	en_US
dc.citation.spage	172	en_US
dc.citation.epage	173	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000247059300078	-
顯示於類別：	會議論文