標題: | A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist |
作者: | Lien, Nan-Chun Chu, Li-Wei Chen, Chien-Hen Yang, Hao-I. Tu, Ming-Hsien Kan, Paul-Sen Hu, Yong-Jyun Chuang, Ching-Te Jou, Shyh-Jye Hwang, Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Adaptive data-aware write-assist (ADAWA);adaptive voltage detector (AVD);ripple bit-line;Static random-access memory (SRAM);write-ability |
公開日期: | 1-十二月-2014 |
摘要: | This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2x-3.5x variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V. |
URI: | http://dx.doi.org/10.1109/TCSI.2014.2336531 http://hdl.handle.net/11536/123869 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2014.2336531 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 61 |
Issue: | 12 |
起始頁: | 3416 |
結束頁: | 3425 |
顯示於類別: | 期刊論文 |