完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Fan, Ming-Long | en_US |
dc.contributor.author | Hu, Vita Pi-Ho | en_US |
dc.contributor.author | Hsu, Chih-Wei | en_US |
dc.contributor.author | Su, Pin | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.date.accessioned | 2015-07-21T08:29:05Z | - |
dc.date.available | 2015-07-21T08:29:05Z | - |
dc.date.issued | 2015-01-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2014.2368581 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124041 | - |
dc.description.abstract | This paper investigates the impact of backgate biasing (V-BS) on the drain current (I-D) of ultrathin-body III-V heterojunction tunnel FET (HTFET). Compared with homojunction TFET and III-V/Ge MOSFET, this paper indicates that HTFET exhibits significantly higher I-OFF (I-D at V-GS = 0 V and V-DS = 0.5 V) modulation efficiency and the influence of VBS rapidly decreases with increasing V-GS. In addition, it is observed that the change of source available states with VBS determines the I-D modulation efficiency of p-type HTFET (pHTFET). Depending on the source doping concentration and operating V-GS, the I-D of HTFET under forward V-BS can be anomalously smaller than that at V-BS = 0 V. Furthermore, the impacts of source/drain doping concentrations and junction properties are discussed and shown to be critical in determining the I-D modulation efficiency of HTFET. We find that, under controlled ambipolar current, reverse backgate biasing can be utilized to suppress the I-OFF of HTFET, and the modulation efficiency increases with decreasing source doping concentration. Our study may provide insights for device/circuit designs with advanced TFET technologies. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Backgate biasing | en_US |
dc.subject | heterojunction tunnel FET (HTFET) | en_US |
dc.subject | ultrathin-body (UTB) structure | en_US |
dc.title | Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2014.2368581 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 62 | en_US |
dc.citation.spage | 107 | en_US |
dc.citation.epage | 113 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000346979800016 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |