鰭狀、穿隧場效電晶體和異質通道三維積體超薄層元件於超低功耗靜態隨機存取記憶體和邏輯電路之設計與分析

Abstract

本論文針對微縮鰭狀場效電晶體(FinFET)、穿隧場效電晶體(Tunnel FET)以及異質通道三維積體超薄層元件(Hetero-Channel UTB Device)在超低功耗應用提供完整的評估與分析。在此論文中，我們考慮元件-電路間相互影響(interaction)和共同最佳化(co-optimization)以呈現上述元件在元件/電路層面的潛力以及隱憂。藉由本研究，我們探討元件變異度以及低操作電壓對於邏輯電路(Logic Circuits)的漏電-延遲和靜態隨機存取記憶體(SRAM)的穩定度-效能的影響以提供未來低電壓操做電路設計藍圖。 由於其優異的靜電完整性(electrostatic integrity)和變異免疫能力(variability immunity)，我們透過解析解的方式分析次臨界(subthreshold)鰭狀場效電晶體靜態隨機存取記憶體的靜態雜訊邊界(static noise margin)。在檢視幾個藉由獨立閘極控制設計的6T鰭狀場效電晶體靜態隨機存取記憶體的穩定度後，我們發現這些記憶體單元擁有較佳的讀取靜態雜訊邊界的提升。然而，某些記憶體單元在寫入能力的惡化將限制次臨界操作的穩健程度(robustness)。和傳統調整元件尺寸的方式相比，讀取/寫入字元線電壓控制技術(READ/WRITE word-line voltage control technique)可較有效率地提升次臨界記憶體的穩定度。此外，我們提出以模型為基礎的架構同時考慮多種變異來源(variation source)且有效率的分析元件變異對於記憶體單元穩定度的影響。和功函數變異(Work-Function Variation)相比，我們發現鰭線邊緣粗糙(fin Line-Edge-Roughness)是造成次臨界電流擾動的主要原因。透過已建立的模型架構，我們檢視元件變異對於傳統6T以及新提出4T記憶體單元的影響。因為讀取干擾(READ disturb)的降低和趨近理想的VWRITE,0和VWRITE,1，4T記憶體單元分別擁有較佳的讀取和寫入靜態雜訊邊界。在相同記憶體單元面積考量之下，4T單元因為有較少的電晶體數目可適度放寬元件尺寸以及提供較6T單元優異的讀取靜態隨機邊界變異。另一方面，由於其立體的元件結構以及在量子侷促(quantum confinement)效應的差異，鰭狀場效電晶體傳統(110)電流的導通方向可藉由電路佈局(layout)旋轉而提升記憶體單元的穩定度。和(100)晶向(surface orientation)相比，我們發現NFET在(110)晶向有較大鰭線邊緣粗糙造成臨界電壓(threshold voltage)的變異；而PFET則表現出相反的趨勢。因此，透過電晶體晶向的最佳化，(110,100,100)記憶體單元擁有最佳的讀取靜態雜訊邊界並揭露6T鰭狀場效電晶體記憶體單元在次臨界應用的潛力。 除了記憶體單元，我們亦考慮了元件變異對於小訊號差動(small-signal differential)和大訊號單端(large-signal single-ended)次臨界鰭狀場效電晶體記憶體單元感測方式(sensing scheme)的影響。在本論文中，選取記憶體單元(selected cell)的本質變異、在選取位元線上(selected bit-line)其他未選取記憶體單元(unselected cell)的漏電流(及其變異)以及感測放大器(sense amplifier)抵銷電壓(offset voltage)和轉變電壓(trip voltage)的變異都將同時被考慮。對於小訊號差動感測方式而言，其次臨界感測邊界(sensing margin)被位元線變異嚴重地降低使得我們需要較長的時間去啟動感測放大器。對於大訊號感測方式，我們發現在感測邏輯0以及邏輯1訊號時有明顯的差異且較差的邏輯0感測邊界將會限制每位元線所能容許的記憶體單元數量以及感測效能。藉由模型輔助，我們發現由臨界電壓差異(threshold voltage mismatch)計算得到電流栓鎖感測放大器(Current-Latch Sense Amplifier)的抵銷電壓被低估且得到過於樂觀的預測。和傳統BULK金氧半場效電晶體(MOSFET)相比，鰭狀場效電晶體提升了小訊號差動感測方式在次臨界靜態隨機存取記憶體應用的可行性。 在低電壓操作時，隨機電報雜訊(Random Telegraph Noise)的重要性隨之增加也威脅到電路的功能性(functionality)。我們探討單一缺陷捕捉(trap)造成的隨機電報雜訊對於鰭狀場效電晶體元件、6T靜態隨機存取記憶體單元和邏輯電路的影響。我們研究指出當帶電的界面缺陷捕位於電晶體的底側以及源極(source)汲極(drain)中間時有最大的影響力。此外，等效氧化層厚度(equivalent oxide thickness)微縮以及高操作溫度可提升隨機電報雜訊的免疫能力。和具有較低元件變異以及內部導通(volume conduction)特性的鰭狀場效電晶體相比，BULK金氧半場效電晶體較差的變異免疫力和表面導通特性造成較大的分布以及最差(worst-case) 隨機電報雜訊。在考量隨機電報雜訊的影響下，鰭狀場效電晶體反相器(inverter)、NAND閘和二對一多工器(multiplexer)在漏電流以及延遲在0.4伏特操作電壓時分別造成 ~24% - 27%和~ 13% - 15%額外的變異。 透過能帶間穿隧效應(band-to-band tunneling)所產生的電流，穿隧場效電晶體(Tunnel FET)由於其克服熱電子(thermionic)限制的能力以及更為優異的切換特性被視為在未來超低電壓操作應用極具競爭力的元件。我們廣泛地研究單一受體型態(acceptor-type)或施體型態(donor-type)介面缺陷捕捉造成的隨機電報雜訊對於穿隧場效電晶體元件、靜態隨機存取記憶體電路以及和功函數變異的相互影響。我們發現當受體型態缺陷捕捉位於穿隧接面(tunneling junction)時有較大的影響而對於施體型態缺陷捕捉而言，其具有顯著影響力的範圍更為廣泛。此外，像是可用以提升穿隧場效電晶體次臨界特性的元件參數(例如:薄等效氧化層厚度、薄鰭寬度(fin width)和較長的通道長度)被發現會惡化隨機電報雜訊。在考量功函數變異下，穿隧場效電晶體的導通電流以及漏電流的相依程度較鰭狀場效電晶體低。取決於缺陷捕捉的型態以及金屬閘極晶粒的組成和晶向，功函數變異的存在可提升亦或者降低隨機電報雜訊的影響。此外，我們研究發現隨機電報雜訊分別對於標準8T靜態隨機存取記憶體的穩定度以及電流栓鎖感測放大器的抵銷電壓造成~16% 穩定度(在0.3伏特操作)以及80毫伏特抵消電壓(在0.5伏特操作)的影響。 藉由單石三維整合(monolithic 3D integration)，我們廣泛地探討異質通道邏輯電路和6T/8T靜態隨機存取記憶體在低功耗應用面的優點。透過適當的三維電路佈局，我們可達成和使用兩種不同背閘極偏壓(backgate bias)二維電路相同的最小漏電流。和二維電路相比，由於層間電性耦合的存在，單石三維反相器、Two-Way NAND閘、多工器、靜態栓鎖器(static latch)和資料正反器(D Flip-Flop)具有可觀的效能提升特別是以絕緣鍺(GeOI)元件為基石的邏輯電路在低電壓操作時。在幾種不同層電晶體閘極對準記憶體單元的佈局設計下，我們評估雙層6T/8T記憶體單元的穩定度/效能。我們發現堆疊NFET層在PFET層之上具有較大穩定度以及效能的設計空間。由於其優異效能和穩定度的提升，單石三維堆疊搭配異質通道電晶體是較佳的設計選項。 本論文也涵蓋背閘極偏壓對於三五族超薄層異質接面穿隧場效電晶體(III-V UTB Heterojunction TFET)汲極電流的影響以及單石三維穿隧場效電晶體靜態隨機存取記憶體單元的設計。和等質接面(homojunction)穿隧場效電晶體以及傳統電晶體相比，我們研究顯示異質接面穿隧場效電晶體具有極高的漏電流調變能力(IOFF modulation efficiency)以及背閘極偏壓的影響力隨著閘極電壓的提高急劇的降低。此外，我們亦發現源極端可容納的量子態(allowable state)隨著背閘極偏壓改變影響到p型異質接面穿隧場效電晶體的電流調變能力。取決於源極摻雜濃度以及閘極操作電壓，異質接面穿隧場效電晶體順偏偏壓下的汲極電流可異常地小於無背閘極偏壓的電流。由於層間電性偶合的差異，我們透過電路佈局最佳化標準全穿隧場效電晶體(standard all-TFET)和我們新提出混合(hybrid) 8T靜態隨機存取記憶體單元在二維和三維整合設計時的比較。

This dissertation provides an extensive assessment of nanoscale FinFET, Tunnel FET (TFET) and hetero-channel 3D integrated Ultra-Thin-Body (UTB) MOSFET for ultra-low-power applications. Device-circuit interactions and co-optimizations are considered to demonstrate the potential and concerns of these emerging devices from the device/circuit point of view. Through our analysis, the impacts of device variability and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAM cells are evaluated to offer insights for future low-voltage circuit designs. With the superior electrostatic integrity and variability immunity of FinFET devices, the Static Noise Margin (SNM) of subthreshold FinFET SRAM cells is investigated using an analytical SNM model. Examination of the stabilities of several novel 6T FinFET cells using independent-gate technique indicates significant improvements in nominal READ SNM (RSNM) in these cells. However, the WRITE ability is found to be degraded and limits the cell robustness for certain cells in the subthreshold region. The READ/WRITE word-line voltage control technique is found to be more effective than transistor sizing in enhancing the stability of subthreshold FinFET SRAM cell. In addition, a model-assisted approach is developed to account for multiple variation sources simultaneously and efficiently when investigating the impact of device variability on the cell stability. Compared with Work-Function Variation (WFV), our results indicate that fin Line-Edge-Roughness (fin LER) dominates the overall subthreshold drain current fluctuation. With the established model approach, two recently introduced 4T and conventional 6T FinFET SRAM cells are statistically examined. Because of the reduced READ disturb, the 4T cells exhibit better nominal RSNM and the nearly ideal VWRITE,0 and VWRITE,1 of 4T cells promise the positive nominal WRITE SNM (WSNM) for selected cells. Under identical cell area, 4T SRAM cells with fewer transistors have the flexibility to increase device size (reduced σRSNM) and outperform the 6T counterpart. On the other hand, because of its vertical topology and difference in the degree of quantum confinement, the conventional sidewall conducting (110) surface orientation of FinFET can be rotated by layout to improve cell variability. It is found that NFET with (110) orientation shows larger fin LER induced threshold-voltage variation than the (100) one, while PFET exhibits the opposite trend. Therefore, with optimal orientations, significant μ/σ ratio improvement in RSNM can be achieved by using SRAM cell with (PU,PD,PG) = (110,100,100), revealing the potential of 6T FinFET cells with appropriate optimization for emerging subthreshold FinFET SRAM applications. In addition to cell, the viability and merits of small-signal differential sensing and large-signal single-ended sensing schemes for FinFET SRAM are investigated under the influence of variability. The local random variation of selected cell, leakage (and its variation) from unselected cells on the selected bit-line, and variation of sense amplifier offset voltage (VOS) and trip voltage (VTRIP) are considered simultaneously. For differential sensing scheme, the subthreshold sensing margin is severely degraded by the variation in bit-line voltage and sufficient time before enabling the sense amplifier is required. For large-signal sensing scheme, we show that there is large disparity between the sense “0” margin and sense “1” margin with significantly worse sense “0” margin limiting the affordable number of cells per bit-line and performance. Using our statistical model-based approach, it is observed that the VOS of Current-Latch Sense Amplifier (CLSA) calculated solely from threshold-voltage mismatch underestimates the actual variation and is shown to be optimistic. Compared with the conventional BULK MOSFET, FinFET enhances the feasibility of differential sensing in subthreshold SRAM applications. Under low-VDD design, the importance of Random Telegraph Noise (RTN) increases and threats the functionality of circuits. We analyze the impact of single-trap-induced RTN on FinFET devices, 6T SRAM cell, and several logic circuits. Our result indicates that the charged interface trap located near the bottom and middle region between source/drain results in most significant impact. Besides, Equivalent Oxide Thickness (EOT) scaling and higher operating temperature are found to improve the immunity to RTN. The larger variability and surface conduction of planar BULK MOSFET lead to broader dispersion and larger worst-case RTN degradation than the FinFET with smaller variability and volume conduction. In the presence of RTN, ~ 24% - 27% and ~ 13% - 15% additional variations in the leakage and delay, respectively, are observed at VDD = 0.4V for the FinFET inverter, Two-Way NAND and Two-To-One multiplexer. Using band-to-band tunneling as major conduction mechanism, Tunnel FET (TFET) with capability to surmount the thermionic limitation and provide superior switching characteristics is regarded as promising candidate for ultra-low-voltage operation. We extensively investigate the impacts of single acceptor-type or donor-type interface trap induced RTN on TFET device, SRAM circuits and its interaction with WFV. In our analysis, significant RTN amplitude is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. Moreover, several device parameters which can improve the TFET subthreshold characteristics (e.g. thinner EOT, fin width or longer channel length) are found to increase the susceptibility to RTN. Under WFV, TFET exhibits weaker correlation between ION and IOFF than that in the FinFET. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of trap and composition/orientation of metal-gate grain. In addition, our analysis indicates that ~ 16% extra variation (at VDD = 0.3V) in the stability of standard 8T SRAM cell and ~80mV additional VOS variation (at VDD = 0.5V) for the CLSA circuit are observed. The advantages of hetero-channel logic circuits and 6T/8T SRAM cells for low-power applications are comprehensively evaluated with monolithic 3D integration. With adequate 3D layout design, minimum leakage, equivalent to the planar 2D circuits with dual backgate biases (VBS), is achievable. Furthermore, with interlayer coupling, substantial performance improvements over the 2D counterparts are found for monolithic 3D inverters, Two-Way NAND, multiplexer, static latch and D Flip-Flop, especially for GeOI logic circuits operating in low VDD. Besides, various bit-cell layouts with different gate alignments of transistors from distinct layers are investigated for the evaluation of cell stability/performance of two-tier 6T/8T SRAM cells. Our studies indicate that stacking the NFET tier over the PFET layer results in larger design margins for cell robustness and performance. The larger improvements over the 2D counterparts make hetero-channel 3D integrated MOSFET a suitable candidate for monolithic 3D applications. For III-V UTB Heterojunction TFET (HTFET), the impact of VBS on the drain current and implications/designs for monolithic 3D SRAM cells are assessed. Compared with homojunction TFET and conventional MOSFET, our results indicate that HTFET exhibits significantly higher IOFF modulation efficiency and the influence of VBS rapidly decreases with increasing gate voltage. In addition, it is observed that the change of source available states with VBS determines the ID modulation efficiency of p-type HTFET. Depending on the source doping and operating VG, the ID of HTFET under forward VBS can be anomalously smaller than that at VBS = 0V. With the difference in the efficiency of interlayer coupling, the standard all-TFET and our proposed hybrid 8T SRAM cells are optimized with layouts and compared in 2D/3D integrations.