超薄層矽及鍺通道元件、邏輯電路及靜態隨機存取記憶體之研究與分析

Abstract

超薄層矽及鍺通道元件(如Ultra-Thin-Body Silicon-On-Insulator (SOI), Germanium-On-Insulator (GeOI), and FinFET元件)，由於其對短通道效應有較佳的控制能力及較小的變異度，使其成為未來CMOS技術可實行的元件。然而，除了這些前瞻元件在元件特性上的研究外，鮮少有此先進元件在電路上的影響之研究，本篇論文主要在分析探討極微縮超薄層矽和鍺通道元件，及其對於邏輯電路(Logic circuits)和靜態隨機存取記憶體(SRAM cells)的影響及分析。

首先，我們提出了一個具預測性及微縮性的解析模型來分析超薄層鍺通道元件的靜電完整性(electrostatic integrity)，我們也考慮不同的深埋絕緣層(buried insulator, 如GeOI 及GeON)對超薄層鍺通道元件的靜電完整性之影響。接著我們對超薄層鍺通道元件在邏輯電路及靜態隨機存取記憶體的漏電、效能、穩定度及變異度之影響，做了完整的研究，並與其相對應的超薄層矽通道元件電路做比較。研究發現超薄層鍺通道元件能利用堆疊元件(stacking transistors)來降低其漏電(band-to-band tunneling)，然而Bulk鍺通道元件則無法利用堆疊元件來降低其漏電。在Vdd = 1伏特及400K時，相較於超薄層矽通道元件電路，超薄層鍺通道元件在靜態邏輯電路、動態邏輯電路、閂鎖(latch)及多路復用器(multiplexer)都有較小的延遲(delay)。在相同的Ion設計下，相較於超薄層矽通道靜態隨機存取記憶體，超薄層鍺通道靜態隨機存取記憶體之穩定度及漏電都有較小的變異性。

本論文也對超薄層矽通道元件在次臨界靜態隨機存取記憶體(subthreshold SRAM)之穩定度及變異度做完整的研究。首先我們提出一個解析模型，能有效率的計算超薄層矽通道靜態隨機存取記憶體在次臨界操作下的穩定度。研究顯示背閘極偏壓(back-gating technique)能較有效的提升次臨界操作下的靜態隨機存取記憶體之穩定度。我們也研究了臨界偏壓(threshold voltage)對於超薄層矽通道靜態隨機存取記憶體之穩定度及變異度的影響，研究顯示利用具有較小的臨界偏壓之元件，能同時提升穩定度及降低變異度，並提供較高的效能。超薄層矽通道元件能比傳統Bulk矽元件在次臨界靜態隨機存取記憶體提供較小的變異度並對溫度有較小的敏感度。我們也發現，超薄層矽通道靜態隨機存取記憶體之變異度主要是受Line-Edge Roughness所影響。

除了本質變異度，我們也發現負/正偏壓溫度不穩定(NBTI/PBTI)所引起的時效性變異會改變最佳化鰭狀電晶體(FinFET)靜態隨機存取記憶體的選擇。我們研究超薄層鰭狀電晶體利用旋轉電晶體的方式來達到降低其本質及時效性的變異度，並考慮了不同的閘極介電層之影響。利用閘極到源極及汲極重疊長度的不對稱性，達到增加讀取穩定度而不會降低其寫入的穩定度，並研究其對效能及變異度的影響。

Ultra-Thin-Body (UTB) Si and Ge-channel MOSFETs (such as UTB Silicon-On-Insulator (SOI), Germanium-On-Insulator (GeOI), and FinFET devices) are viable options for future CMOS technology owing to the superior short-channel control and inherent low device variability due to undoped channel. However, in spite of the extensive research on the device characteristics of these emerging devices, there has not been much analysis from the circuit-level perspective. The goal of this dissertation is to investigate and analyze how these emerging device structures (such as UTB GeOI, UTB SOI and FinFET devices, etc.) impact the leakage, performance, stability and variability of logic circuits and SRAM cells, and provide insights for UTB GeOI, SOI and FinFET devices/circuits design.

First, we assess the electrostatic integrity for nano-scale UTB Ge-channel MOSFETs with various buried insulator permittivity (such as GeOI and Germanium-On-Nothing (GeON)) by using a derived analytical solution of Poisson’s equations that may provide scalable and predictive results for our analysis of UTB GeOI and GeON MOSFETs devices. Based on the investigation of electrostatic integrity for UTB GeOI MOSFETs, we analyze the leakage-delay, stability and variability of UTB GeOI logic circuits and 6T SRAM cells with respect to the SOI counterparts comprehensively. The UTB GeOI circuits show better power-performance than the Bulk Ge-channel circuits, and preserve the leakage reduction property of stacking devices, while the band-to-band tunneling leakage of Bulk Ge-channel devices cannot be reduced by stacking transistors. At Vdd = 1V and 400K, the delays of inverter, dynamic gates, latch and multiplexer for GeOI circuits are smaller than the SOI counterparts. For equal Ion design, the GeOI SRAM cells exhibit better 𝝁RSNM/σRSNM and smaller cell leakage variation at both Vdd = 1V and 0.5V compared with the SOI SRAM cells.

We have also conducted research on the UTB SOI SRAM cells operating in the subthreshold region including the investigation of stability, performance, leakage and variability for 6T/8T UTB SOI subthreshold SRAM cells. An analytical framework to calculate the Static Noise Margin (SNM) for UTB SOI subthreshold SRAM cells is presented to efficiently investigate the Read/Write stability (RSNM/WSNM). The results indicate that for both the RSNM and WSNM improvement, the back-gating technique is more effective in the subthreshold mode than in the superthreshold mode. The impact of threshold voltage design on the UTB SOI SRAM cells operating near the subthreshold region is also investigated. The lower threshold voltage devices operating slightly into superthreshold region improve the stability/variability significantly and offer higher performance for ultra-low voltage SRAM applications. The intrinsic advantages of UTB SOI technology versus Bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are also demonstrated. The RSNM of UTB SOI subthreshold SRAM cells show smaller variability and less temperature sensitivity compared with that of Bulk subthreshold SRAMs. Due to the very small subthreshold swing fluctuations, Work Function Variation (WFV) shows less impact on the variability of UTB SOI subthreshold SRAMs, and the variability of UTB SOI subthreshold SRAMs is dominated by Line-Edge Roughness (LER). Our results indicate that the 6T UTB SOI subthreshold SRAM cells with back-gating technique and threshold voltage design may adequately meet/support the stability, leakage/density, and frequency requirements for intended application space of subthreshold SRAMs.

In addition to the intrinsic process variation, we demonstrate that the negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations change the optimal choice of FinFET SRAM cell surface orientations in term of the μ/σ ratio in RSNM. The combined effects of time-zero intrinsic process variability and long-term temporal variability (due to NBTI/PBTI) are considered for optimizing the FinFET device orientation combinations to improve the stability/variability of 6T FinFET SRAM cells with oxide and high-K gate dielectrics, respectively. We also investigate the 6T FinFET SRAM cells using asymmetric gate-to-source/drain underlap device to improve RSNM without degrading WSNM, and the resulting impacts on performance and variability. The conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors.