超薄絕緣層異質三五族與鍺通道金氧半場效電晶體及單層與多層二維過渡金屬硫屬化合物之邏輯電路及靜態隨機存取記憶體之研究與分析

Abstract

本論文針對新穎的超薄絕緣層異質三五族與鍺通道金氧半場效電晶體的可微縮性與二維過渡金屬硫屬化合物(2-D transition-metal dichalcogenide)構成之邏輯電路(logic circuits)及靜態隨機存取記憶體(SRAMs)性能及穩定性提供完整的評估與分析。在此論文中，我們考慮元件-電路間相互影響(interaction)和共同最佳化(co-optimization)以呈現二維過渡金屬硫屬化合物元件在元件/電路層面的潛力以及隱憂。藉由本研究，我們探討了量子侷限效應(quantum confinement)、後端閘極調控電性(backgate bias modulation)以及元件變異度(device variability)的影響，以提供未來低電壓操作電路設計藍圖。 藉由研究分析三五族與鍺異質通道超薄絕緣層元件的異常靜電完整性(electrostatic integrity)行為，我們提出了一個未為人所知的本質性物理效應，名為內建之等效基極偏壓效應(built-in effective body-bias effect)。對於異質通道N型電晶體，此效應來自於高載子遷移率通道材料與傳統矽通道材料之間傳導能帶(conduction band)的偏移量，此偏移量由電子親和力(electron affinity)的差距以及等效傳導能帶的能態密度(effective density-of-state of conduction band)的差異所構成。而對於異質通道P型電晶體，此效應則是來自於高載子遷移率通道材料與傳統矽通道材料之間價帶(valence band)的偏移量，對於鍺通道P型電晶體而言，這價帶偏移量主要來自於能隙(band-gap)的差異。從靜電完整性的觀點來說，此內建等效基極偏壓效應對於絕大多數的超薄絕緣三五族N型電晶體(III-V-OI nFETs)與超薄絕緣鍺P型電晶體(GeOI pFET)是一個有害的效應，其會使靜電完整性比由介電係數(permittivity)所預期的更加惡化。此外，內建等效基極偏壓效應對靜電完整性的影響的重要性並不亞於介電系數。我們的研究還指出，由於內建等效順向基極偏壓效應使得靜電完整性惡化，超薄絕緣砷化銦鎵N型電晶體與超薄絕緣鍺P型電晶體也會因此具有比超薄絕緣鍺N型電晶體更差的臨界電壓(threshold-voltage, VT)變異度。相關的通道長度、等效氧化層厚度、通道厚度與埋藏氧化層厚度與內建等效基極偏壓效應對於靜電完整性的影響之相依性也有所探討分析。所以當一對一比較這些超薄絕緣層異質通道電晶體的靜電完整性時，這個本質性的內建等效基極偏壓效應需要被納入考量。 量子侷限效應的影響隨著通道厚度的微縮而益發重要。藉由使用薛丁格方程式(Schrödinger equation)的解析解與元件數值模擬進行交相驗證，我們理論性地研究探討量子侷限效應對於元件靜電完整性以及本質臨界電壓變異度的影響。除此之外，考慮量子侷限效應後，後端閘極調變之靜電完整性以及臨界電壓變異度會受到何種影響也有研究分析。我們的研究指出，儘管異質通道元件受到高介電係數與順向的內建等效基極偏壓效應影響，其載子密度分布極可能會遠離前端閘極介面，但量子侷限效應卻會使載子重心靠近前端閘極，因此異質通道元件的靜電完整性像是汲極誘發能障降低(DIBL)與次臨界擺幅(subthreshold swing)可以被改善而變得與矽元件差不多。除此之外，對於超薄絕緣層異質三五族與鍺通道元件，量子侷限效應也會抑制其靜電完整性以及本質臨界電壓變異度對製程與溫度變異的後端閘極相依性。換而言之，當後端閘極被應用作功耗性能最佳化(power-performance optimization)或是全體變異度的修正補償(global variability compensation)時，量子侷限效應可以抑制同一晶粒內(within-die)的臨界電壓變化。因為不同的量子化有效質量，三五族、鍺與矽通道顯示出不同的量子侷限程度，所以當一對一比較這些超薄層異質通道元件時，量子侷限效應的影響也必須納入考量。本論文希望在使用這些先進的超薄絕緣層異質通道工藝技術時，能夠提供對於多臨界電壓元件與電路設計(multi-VT device/circuit designs)更多的了解。 對於未來終極微縮互補式金屬氧化物半導體(CMOS)元件，由於其超薄的原子層級材料厚度，二維層狀過渡金屬硫屬化合物材料已經成為具有潛力的候選通道材料之一。針對國際半導體技術發展路線圖2028年技術節點，本論文廣泛地研究評估由單層與雙層二維過渡金屬硫屬化合物構成的邏輯電路之性能表現以及靜態隨機存取記憶體的性能與穩定性。對於靜態互補式金屬氧化物半導體邏輯(static CMOS logic)家族，我們發現單層與雙層邏輯電路具有差不多的延遲時間，即使雙層二維過渡金屬硫屬化合物元件具有較高的載子遷移率。另一方面，對於開關電晶體邏輯(pass-transistor logic)家族，相比單層開關電晶體邏輯電路，雙層開關電晶體邏輯電路具有較長的延遲時間，特別是那些使用單獨N型電晶體而非傳輸閘極(transmission gate)作為訊號傳遞開關的開關電晶體邏輯電路，像是現場可程式閘陣列(field programmable gate array, FPGA)裡的可程式之路由控制開關(programmable routing switches)。除外，因為有比較好的靜電完整性，我們也發現單層二維過渡金屬硫屬化合物組成之靜態隨機存取記憶體，相對雙層靜態隨機存取記憶體而言，擁有較佳的讀取靜態雜訊邊界(read static noise margin, RSNM)、較差的寫入靜態雜訊邊界(write static noise margin, WSNM)以及差不多的讀取寫入效能。除了以上，本質隨機變異在超臨界(super-threshold)與近臨界/次臨界(near-/sub-threshold)操作下對靜態隨機存取記憶體的穩定性影響也在本論文中有所討論。對於6T靜態隨機存取記憶體，由於嚴重的金屬閘極功函數變異(work function variation)，單層過渡金屬硫屬化合物所構成之靜態隨機存取記憶體在超臨界操控下還有可能提供足夠的免疫能力，但在近臨界/次臨界操控下，不論單層抑或雙層靜態隨機存取記憶體皆無法有足夠的變異免疫力。此外，過高的源極/汲極串聯電阻 (source/drain series resistance, RSD)一直被視為二維過渡金屬硫屬化合物元件的主要隱憂，我們發現其會使單層與雙層超臨界靜態隨機存取記憶體的讀取靜態雜訊邊界平均值對標準差的比率(/ ratio)下降惡化，但對於近臨界/次臨界靜態隨機存取記憶體卻基本上沒有影響；意謂著對於超低功耗物聯網(internet-of-things, IoT)應用，較高的源極/汲極串聯電阻比較不是問題。為了改善嚴重的變異度影響，8T靜態隨機存取記憶體架構可能會有幫助而被使用，我們的研究發現，在8T架構下，單層與雙層近臨界/次臨界靜態隨機存取記憶體皆顯示大幅改善的變異免疫力。根據我們的評估，因為其具有相當良好的靜電完整性，單層過渡金屬硫屬化合物元件比較適合低功耗的邏輯電路與靜態隨機存取記憶體應用；而雙層過渡金屬硫屬化合物元件，因為具有較高的載子遷移率，比較適合高性能的邏輯電路與靜態隨機存取記憶體應用。 我們對於二維過渡金屬硫屬化合物構成之邏輯電路與靜態隨機存取記憶體的研究不僅僅停留在平面式技術，也擴展到單石三維整合(monolithic 3-D integration)的層面。藉由單石三維整合技術所賦予的分別採用單層或多層二維過渡金屬硫屬化合物於N型電晶體層(nFET-tier)與P型電晶體層(pFET-tier)之可能性，我們的研究指出，即使其載子遷移率高出單層與雙層過渡金屬硫屬化合物元件不少，使用三層過渡金屬硫屬化合物元件於N型電晶體層或P型電晶體層依然會使邏輯電路之性能大幅下降，這是由於其過差的汲極誘發能障降低與次臨界擺幅。對於單石三維6T超臨界靜態隨機存取記憶體，相比平面式技術，於雙層過渡金屬硫屬化合物N型電晶體層之上堆疊單層過渡金屬硫屬化合物P型電晶體層可以提供較佳的穩定性以及讀取/寫入速度。而最佳的三維6T近臨界/次臨界靜態隨機存取記憶體設計組態則是於單層過渡金屬硫屬化合物N型電晶體層之上堆疊單層過渡金屬硫屬化合物P型電晶體層。而由於8T靜態隨機存取記憶體具有近乎理想的讀取穩定度，所以最佳的三維8T近臨界/次臨界靜態隨機存取記憶體設計組態是於雙層過渡金屬硫屬化合物P型電晶體層之上堆疊單層過渡金屬硫屬化合物N型電晶體層。

This dissertation provides an extensive assessment of the scalability of the exploratory ultra-thin-body (UTB) III-V/Ge hetero-channel MOSFETs and the performance/stability of 2-D transition-metal-dichalcogenide (TMD) based logic circuits and SRAM cells. Device-circuit interactions and co-optimizations are considered to demonstrate the potential and concerns of the emerging TMD hetero-channel devices from the device/circuit point of view. Through our analysis, the impacts of quantum confinement, backgate biasing, and device variability are investigated to offer insights for future low-voltage device/circuit designs. A new intrinsic mechanism “built-in effective body-bias (VBS,eff) effect” related to the vertical backgate coupling in UTB hetero-channel GeOI and III-V-OI MOSFETs is reported and quantified to be responsible for the anomalous electrostatic integrity (EI) behaviors which violate the expectation of permittivity. For hetero-channel n-MOSFETs, this effect results from the conduction band offset (composed of discrepancies in electron affinity and the effective density-of-states of conduction band) between the high-mobility channel and conventional Si channel. For hetero-channel p-MOSFETs, this effect stems from the valence band offset (which mainly comes from the discrepancies in channel band-gap for Ge pFETs). From the perspective of electrostatic integrity, the built-in effective body-bias effect is shown to be a detrimental effect (whose impact can be comparable to that of permittivity) for most III-V-OI nFETs and the GeOI pFET, and thus the device electrostatics can be worse than what permittivity predicts. In addition, it is shown that the In0.53Ga0.47As-OI nFET and GeOI pFET may possess worse threshold-voltage (VT) variability than the GeOI nFET counterparts due to the aggravated EI by the built-in forward VBS,eff effect. The L-, EOT-, Tch-, TBOX-dependences of the impact of built-in VBS,eff on device electrostatics are also examined and discussed. This intrinsic effect has to be considered when one-to-one comparisons among various UTB hetero-channel MOSFETs regarding the electrostatic integrity are made. The quantum confinement effect becomes critical as channel-thickness keeps scaling down, and its impacts on the device electrostatic integrity and the intrinsic VT variability are theoretically investigated through an analytical solution of Schrödinger equation corroborated with TCAD numerical simulation. Besides, the backgate-bias modulated electrostatic integrity (including drain-induced-barrier-lowering (DIBL), subthreshold swing, and VT roll-off) and VT variability considering qunatum confinement are also analyzed. Our study indicates that albeit the carrier density distribution of the hetero-channel device can be far from the frontgate interface due to the high channel permittivity and the built-in forward body-bias effect, the quantum-confinement effect can move the carrier centroid toward the frontgate, and therefore the device EI such as DIBL and subthreshold swing can be improved and becomes comparable to the Si device. Moreover, the quantum confinement effect lessens the backgate-bias dependences of device electrostatic integrity and the intrinsic VT variability to process and temperature variations for UTB III-V/Ge hetero-channel devices. In other words, the backgate-bias dependence of the within-die VT variation can be suppressed by the quantum confinement effect as the backgate bias is used for power-performance optimization or global variability compensation. Since III-V, Ge and Si channels exhibit different degree of quantum confinement due to different quantization effective mass, the impact of quantum confinement has to be considered when one-to-one comparisons among the hetero-channel devices regarding electrostatic and intrinsic variability are made. Our study may provide insights for multi-VT device/circuit designs using advanced UTB technologies. 2-D layered TMD materials have emerged as promising channel materials for future ultimately-scaled CMOS devices due to the atomic-scale body thickness. We extensively evaluate the performance of logic circuits and the stability/performance of SRAM cells using mono-layer and bi-layer TMD devices based on ITRS 2028 (5.9nm) technology node. For the static CMOS logic family, albeit the bi-layer TMD devices possess higher mobility than the mono-layer counterpart, the mono-layer and bi-layer static CMOS logic circuits may show comparable delay time. On the other hand, for the pass-transistor logic family, the bi-layer pass-transistor logic circuits may exhibit much slower delay time that the mono-layer ones counterparts, particularly for those using single nMOS pass-gate transistors instead of transmission gate as signal propagation switches (e.g., the programmable routing switches in FPGAs). In the SRAM evaluations, the mono-layer MoS2-n/WSe2-p SRAM, with superior device electrostatics, is shown to exhibit larger read static noise margin (RSNM), smaller write static noise margin (WSNM), and comparable read/write performance compared with the bi-layer counterparts. Besides the nominal evaluations, the impacts of intrinsic random variations on the cell stability of 6T/8T TMD based SRAM cells for super-threshold and near-/sub-threshold operations are also conducted. Our study indicates that, for 6T SRAM, due to severe metal gate work function variation (WFV) stemming from the tiny gate area, the mono-layer SRAMs may offer sufficient immunity under super-threshold operation, while both the mono-layer/bi-layer near-/sub-threshold SRAMs exhibit unacceptable RSNM variability in spite of the excellent electrostatics of mono-layer TMD devices. Besides, high source/drain series resistance (RSD) as a major concern of TMDs may degrade the / ratios for mono-layer and bi-layer super-threshold SRAMs, whereas it should be less of an issue for near-/sub-threshold SRAMs for ultra-low power internet-of-things (IoT) applications. The standard 8T SRAM cell with the capability of elimination of read disturb may be utilized to improve the noise margin for variation tolerance. Our results show that the RSNM variations due to WFV of both mono-layer and bi-layer near-/sub-threshold SRAMs can be significantly improved by using 8T cell structure, and thus the 6 RSNM yield requirement can be met. Based on our evaluation, due to the excellent device electrostatics stemming from its single atomic layer, the mono-layer TMD devices are favored for low-power logic and SRAM applications; while the bi-layer devices, with higher carrier mobility, are more suitable for relaxed channel length and high-performance logic and SRAM applications. Our research in TMD based logic circuits and SRAM cells is also extended from planar technology to monolithic 3-D integration. The performance of 3-D logic circuits and performance/stability of 3-D 6T SRAM cells using mono- and few-layer TMD devices are comprehensively evaluated and benchmarked against the planar technology. With the possibility of adopting mono-layer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, our study indicates that using the tri-layer devices for nFET- or pFET-tiers may substantially degrade the performance of logic circuits (compared with the planar technology and other 3-D combinations) due to worse subthreshold swing and DIBL even though their mobilities are much higher. For monolithic 3-D 6T SRAMs, stacking the mono-layer pFET-tier over the bi-layer nFET-tier can provide superior stability and read/write performance for 6T super-threshold SRAM cells compared with the planar technology. However, the optimum 3-D configuration for 6T near-/sub-threshold SRAM cell appears to be the mono-layer pFET-tier over the mono-layer nFET-tier. Besides the 6T cell structure, Monolithic 3-D 8T SRAM cells are also investigated under near-/sub-threshold operation. The mono-layer nFET-tier over the bi-layer pFET-tier configuration has been shown to be the optimum 3-D 8T near-/sub-threshold cell design.