完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Adak, Sarosij | en_US |
dc.contributor.author | Sarkar, Arghyadeep | en_US |
dc.contributor.author | Swain, Sanjit | en_US |
dc.contributor.author | Pardeshi, Hemant | en_US |
dc.contributor.author | Pati, Sudhansu Kumar | en_US |
dc.contributor.author | Sarkar, Chandan Kumar | en_US |
dc.date.accessioned | 2015-07-21T11:20:33Z | - |
dc.date.available | 2015-07-21T11:20:33Z | - |
dc.date.issued | 2014-11-01 | en_US |
dc.identifier.issn | 0749-6036 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/j.spmi.2014.07.036 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124128 | - |
dc.description.abstract | In the present work, we propose and perform extensive simulation study of the novel device structure having a p-GaN back barrier layer inserted in the conventional AlInN/AlN/GaN Gate-Recessed Enhancement-Mode HEMT device for reducing the short channel effects, gate leakage and enhancing the frequency performance. The influence of the p-GaN back barrier layer on the device performance of the newly proposed structure is done using 2D Sentaurus TCAD simulations. The simulations use Drift Diffusion (DD) model, Masetti and Canali model, which are calibrated/validated with the previously published experimental results. Simulation are done to analyze the transfer characteristics, transconductance (g(m)), Gate leakage current (I-g), drain induced barrier lowering (DIBL), subthreshold slope (SS), threshold voltage (Vth), On-current Off-current ratio (I-on/l(off)), gate capacitance (C-gg) and cut off frequency (f(r)) of the proposed device. A comparison is done between the device without back barrier layer and the proposed device with p-GaN back barrier layer. Use of p-GaN back barrier layer helps to achieve a higher positive Vth due to the depletion effect, reduced I-g, reduced DIBL, prevents degradation of SS and helps to increase the f(T). Very impressive f(r) up to 123 GHz, as compared to 70 GHz for the device without back barrier. These results indicate that AlInN/AlN/GaN Gate-Recessed Enhancement-Mode HEMT structure with p-GaN back barrier is a promising candidate for microwave and switching application. (C) 2014 Elsevier Ltd. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | p-GaN back barrier | en_US |
dc.subject | AlInN/GaN | en_US |
dc.subject | Gate-Recess | en_US |
dc.subject | Enhancement-Mode HEMT | en_US |
dc.subject | Cutoff frequency | en_US |
dc.title | High performance AlInN/AlN/GaN p-GaN back barrier Gate-Recessed Enhancement-Mode HEMT | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1016/j.spmi.2014.07.036 | en_US |
dc.identifier.journal | SUPERLATTICES AND MICROSTRUCTURES | en_US |
dc.citation.volume | 75 | en_US |
dc.citation.spage | 347 | en_US |
dc.citation.epage | 357 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000347017100037 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |