完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChiu, Chao-Changen_US
dc.contributor.authorHuang, Po-Hsienen_US
dc.contributor.authorLin, Morisen_US
dc.contributor.authorChen, Ke-Horngen_US
dc.contributor.authorLin, Ying-Hsien_US
dc.contributor.authorTsai, Tsung-Yenen_US
dc.contributor.authorLee, Chen Chao-Chengen_US
dc.date.accessioned2015-07-21T08:28:48Z-
dc.date.available2015-07-21T08:28:48Z-
dc.date.issued2015-01-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2014.2342380en_US
dc.identifier.urihttp://hdl.handle.net/11536/124227-
dc.description.abstractThe proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.en_US
dc.language.isoen_USen_US
dc.subjectCurrent efficiencyen_US
dc.subjectdigital low dropout (DLDO) regulatoren_US
dc.subjectresistance-locked loop (RLL)en_US
dc.titleA 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvementen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2014.2342380en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume62en_US
dc.citation.spage59en_US
dc.citation.epage69en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000347706500007en_US
dc.citation.woscount0en_US
顯示於類別:期刊論文