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dc.contributor.authorTseng, Chien-Weien_US
dc.contributor.authorWang, Yu-Jiuen_US
dc.date.accessioned2015-07-21T08:29:06Z-
dc.date.available2015-07-21T08:29:06Z-
dc.date.issued2015-02-01en_US
dc.identifier.issn1531-1309en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LMWC.2014.2382682en_US
dc.identifier.urihttp://hdl.handle.net/11536/124341-
dc.description.abstractThis letter reports a fully integrated 60 GHz power amplifier (PA) implemented in TSMC 40 nm CMOS technology. This PA is based on a three-stage two-way differential topology with an output transformer-based power combining network. This topology improves layout symmetry and mitigates parasitic effects between different signal paths to increase overall efficiency. The use of parasitic coupling capacitors inside a vertically-coupled transformer can increase impedance transformation ratio. This PA achieves 20.3 dB power gain, 19.6 dBm output power with 18.3% peak PAE, and 12 GHz bandwidth.en_US
dc.language.isoen_USen_US
dc.subjectClass-Aen_US
dc.subjectcMOS technologyen_US
dc.subjectpower amplifier (PA)en_US
dc.subjectpower combiningen_US
dc.titleA 60 GHz 19.6 dBm Power Amplifier With 18.3% PAE in 40 nm CMOSen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LMWC.2014.2382682en_US
dc.identifier.journalIEEE MICROWAVE AND WIRELESS COMPONENTS LETTERSen_US
dc.citation.volume25en_US
dc.citation.spage121en_US
dc.citation.epage123en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000349778300017en_US
dc.citation.woscount0en_US
Appears in Collections:Articles