A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS

Abstract

A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.