完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Cheng, Ya-Chi | en_US |
dc.contributor.author | Chen, Hung-Bin | en_US |
dc.contributor.author | Su, Jun-Ji | en_US |
dc.contributor.author | Shao, Chi-Shen | en_US |
dc.contributor.author | Thirunavukkarasu, Vasanthan | en_US |
dc.contributor.author | Chang, Chun-Yen | en_US |
dc.contributor.author | Wu, Yung-Chun | en_US |
dc.date.accessioned | 2015-07-21T08:28:32Z | - |
dc.date.available | 2015-07-21T08:28:32Z | - |
dc.date.issued | 2015-02-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2014.2379673 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124578 | - |
dc.description.abstract | This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Junctionless (JL) | en_US |
dc.subject | thin-film transistor (TFT) | en_US |
dc.subject | omega-gate | en_US |
dc.subject | nanowires (NWs) | en_US |
dc.title | Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2014.2379673 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 36 | en_US |
dc.citation.spage | 159 | en_US |
dc.citation.epage | 161 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000350334100025 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |