完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Po-Yi | en_US |
dc.contributor.author | Peng, Shao-Fu | en_US |
dc.contributor.author | Chao, Yu-Chiang | en_US |
dc.contributor.author | Lin, Hung-Cheng | en_US |
dc.contributor.author | Zan, Hsiao-Wen | en_US |
dc.contributor.author | Meng, Hsin-Fei | en_US |
dc.date.accessioned | 2015-07-21T08:29:39Z | - |
dc.date.available | 2015-07-21T08:29:39Z | - |
dc.date.issued | 2015-04-13 | en_US |
dc.identifier.issn | 0003-6951 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1063/1.4917562 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124679 | - |
dc.description.abstract | Vertical organic transistors withstanding high voltage bias were realized with an insulating silicon monoxide layer obliquely deposited on both the surface of the base electrode and sidewalls of the vertically oriented cylindrical nanopores. No noticeable insulating layer can be observed on the emitter electrode at the bottom of the cylindrical nanopores. The leakage current between the electrodes was suppressed and an operating voltage as high as 15V was obtained. An on/off current ratio of 10(3)-10(4) and an output current density of 5-10 mA/cm(2) were achieved. (c) 2015 AIP Publishing LLC. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Vertical organic transistors withstanding high voltage bias | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1063/1.4917562 | en_US |
dc.identifier.journal | APPLIED PHYSICS LETTERS | en_US |
dc.citation.volume | 106 | en_US |
dc.citation.issue | 15 | en_US |
dc.contributor.department | 物理研究所 | zh_TW |
dc.contributor.department | 光電工程學系 | zh_TW |
dc.contributor.department | Institute of Physics | en_US |
dc.contributor.department | Department of Photonics | en_US |
dc.identifier.wosnumber | WOS:000353160700040 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |