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dc.contributor.authorHuang, Ryan H. -M.en_US
dc.contributor.authorHsu, Dennis K. -H.en_US
dc.contributor.authorWen, Charles H. -P.en_US
dc.date.accessioned2015-07-21T08:28:51Z-
dc.date.available2015-07-21T08:28:51Z-
dc.date.issued2015-04-01en_US
dc.identifier.issn0923-8174en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s10836-015-5517-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/124699-
dc.description.abstractSoft errors have been a critical concern for reliability of advanced CMOS designs due to technology scaling. Moreover, along with the rapid growth of medical, automotive, and aerospace electronics, extremely high demand on reliability becomes the paramount concern, superior to cost and performance, on these safety-critical designs. Triple modular redundancy (TMR) is widely used to mask virtually all soft errors but typically incurs high power and area overheads. Therefore, in this paper, a determinate radiation hardened technique for safety-critical CMOS designs is proposed and consists of three hybrid strategies combining gate sizing, supply voltage (V (D D) ) scaling and threshold voltage (V (t h) ) scaling to prevent soft errors from occurring. A STA-like method that computes the required pulse width of a transient fault along the propagation path is also developed in this framework. Simulation results show that the proposed technique can effectively eliminate all soft errors on ISCAS\'85 circuits and a controller area network bus electrical control unit (CAN-bus ECU) design for automotive electronics when the deposited charges range from 35 fC to 132 fC. Furthermore, the strategy using all three techniques, simultaneously improves power and area overheads by 3.3X and 2X, respectively, compared with TMR.en_US
dc.language.isoen_USen_US
dc.subjectSoft error hardeningen_US
dc.subjectSafety critical applicationen_US
dc.subjectReliabilityen_US
dc.subjectTransient fault toleranceen_US
dc.titleA Determinate Radiation Hardened Technique for Safety-Critical CMOS Designsen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s10836-015-5517-5en_US
dc.identifier.journalJOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONSen_US
dc.citation.volume31en_US
dc.citation.spage181en_US
dc.citation.epage192en_US
dc.contributor.department電機資訊學士班zh_TW
dc.contributor.departmentUndergraduate Honors Program of Electrical Engineering and Computer Scienceen_US
dc.identifier.wosnumberWOS:000353472600006en_US
dc.citation.woscount0en_US
Appears in Collections:Articles