安全關鍵應用的設計最佳化以達到零軟性電子錯誤率

Abstract

隨著製程技術的演進，軟性電子錯誤對於先進製程 CMOS 的可靠度 的影響已成為重要的議題。隨著醫療、汽車及航空航天電子等產業的 快速增長，這些安全關鍵應用在可靠度上的需求，相較於成本和效能 考量，已成為第一優先。而TMR 被廣泛的應用於確保零軟性電子錯誤 率，但它通常也導致高功耗和面積方面的負擔。因此，這篇論文針對 安全關鍵應用提出新的零軟性電子錯誤率最佳化的架構。而此架構混 和了三種防止軟性電子錯誤發生的策略，包含了邏輯閘放大、電源電 壓的縮放以及臨界電壓的縮放。此外，我們也發展了改良的STA 演算 法去估計傳遞中的暫態錯誤的所需脈衝寬度。實驗結果顯示，這些混 和式的策略在ISCAS□85 電路以及車用電子的CAN-bus ECU 電路上可 以有效的達到零軟性電子錯誤率。再者，同時使用這三種技術的策略 比TMR 改良了三倍的功耗負擔以及兩倍的面積負擔。

Soft errors have been a critical concern for reliability of advanced CMOS designs due to technology scaling. Moreover, along with the rapid growth of medical, automotive, and aerospace electronics, extremely high demand on reliability becomes the paramount concern, superior to cost and performance, on these safety-critical applications. Triple modular redundancy (TMR) is widely used to ensure zero soft errors but typically incurs high power and area overheads. Therefore, in this paper, a novel zero-SER optimization framework for safety-critical applications is proposed and consists of three hybrid strategies combining gate sizing,supply voltage (VDD) scaling and threshold voltage (Vth) scaling to prevent soft errors from occurring. A modified STA method that computes the required pulse width of transient fault along propagation is also developed in our framework. Experimental results show that these hybrid strategies can effectively achieve zero soft error rates on ISCAS’85 circuits and a CAN-bus ECU design for automotive electronics. Furthermore, the strategy using all three techniques, simultaneously improves power and area overheads by 3X and 2X, respectively, compared with TMR.