針對奈米級CMOS設計電路提出考慮導線效應和老化效應的統計型軟性錯誤率分析的方法

Abstract

老化效應和導線效應以及軟錯誤已經成為用於奈米級CMOS設計中三個最重要的可靠性問題。本篇提出老化效應中負偏壓溫度不穩定性（NBTI）對軟性錯誤的影響，首先採用45nm CMOS技術針對單個元件或整個電路進行軟錯誤分析。其次，導線效應也是造成90nm以下的製程技術造成電路中的軟錯誤的原因,因此軟性錯誤分析必須考慮導線效應的影響。最後，使用了考慮老化效應的模型或導線模型提出準確的統計軟錯誤率（SSER）框架的構建。針對老化效應模型分析的部分，研究結果發現：（1）粒子打在PMOS產生的短暫錯誤與粒子打在NMOS產生的短暫錯誤相比，由於PMOS是更容易受到NBTI效應的影響，使得在PMOS產生的短暫錯誤及其脈衝寬度有更多的變化;（2）NBTI效應和製程變化同時考慮之下，導致更多的軟性錯誤發生（〜19％），因此在電路分析中需要同時考慮NBTI效應和製程變化。另一方面，導線中的電容會使得軟性錯誤率放大，所以導性效應也應該關注。實驗結果說明，在考慮導線效應中電容的影響，以及考慮了製程變化下老化效應對軟性錯誤的影響，我們的SSER框架與蒙地卡羅SPICE模擬相比，除了達到加速的效果，並實現了高精確度的估計（<3％的誤差）。

Aging and interconnect as well as soft errors have become the three most critical reliability issues for nano-scaled CMOS designs. In this work, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, interconnect issue is also considered for soft errors in circuits at 90-nm technology and below. In the end, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models or the wire models. As the result of aging-aware part, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (~19%) and thus needs to be considered, simultaneously, during circuit analysis. On the other hand, the capacitance of wire amplifies soft error rate, so interconnect issue also should be concerned. Experimental result shows that our SSER framework not only considering capacitance of wire but also considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <3% errors) when compared with Monte-Carlo SPICE simulation.