考量軟性延遲並以測試向量為基礎的電路時序分析及其違反時序路徑修正方法

Abstract

現在的電路設計流程中，時序分析(timing analysis)是一個重要的一環，確保了電路穩定的在高速時脈下運作。隨著製程微縮、時脈提升，電路對於高能粒子輻射更加敏感，對於安全優先的應用，例如航太、醫學、車用電子，考慮軟性錯誤(soft error)是必要的，為提升這些應用在高速時脈下穩定運作，所以我們提出一個考量軟性延遲並以測試向量為基礎的電路時序分析稱之為SDPTA。SDPTA可以針對軟性延遲提升電路對於輻射的抵抗能力。根據SDPTA分析電路後的結果，電路會發生違反時序的路徑，因此我們提出修正流程來修這些時序違反路徑。流程中我們提出貪婪法(greedy)及循環法(round robin)，比較這兩個方法調整邏輯閘尺寸減少軟性延遲的表現。我們的實驗結果顯示，軟性延遲所造成時序違反路徑在大多數的電路是可以被修正的，而且循環法在修正路徑的數量上以及面積的使用上皆至少36%優於貪婪法。

In modern VLSI design flow, timing analysis is a critical step to verify if a circuit design could operate at high frequency without errors. As process technology shrinking and clock rate increasing, circuits are more sensitive to radiation-induced particles. For safety applications, soft delay must be considered in timing analysis, thus Soft Delay Pattern-based Timing Analysis is proposed. SDPTA helps designer to enhance their design for reliability or radiation-proved. As designers finish timing closure with Static Timing Analysis (STA), new violations can be exposed after SDPTA. Thus, we propose a path-fixing flow to help designer fix the violation paths. To reduce delays in violation paths, gate sizing technology is included in path-fixing flow with greedy and round robin heuristics. The experimental results show that radiation-induced paths can be fixed in most cases in SDPTA analysis. Overall, the round robin method is better than greedy method in reducing violations and area usage at least 36\% in the improvement.