可防護軟性電子錯誤的閘設計

Abstract

當閘極器件尺寸越來越小，機體電路變得越來越容易受到由輻射粒子所引起的軟性 電子錯誤。軟性電子錯誤包括下列兩種狀態，一個短暫的脈衝可能會傳播到一個存儲單元，且被鎖在儲存單元中（SET），或翻轉儲存在儲存單元中的值（SEU）。軟性電子錯誤可能導致系統故障和不可預知的錯誤。為了消除軟性電子錯誤，許多以往的研究，提出很多觸發器的設計去達到SER 防護。其中一個最先進的BISER 就可同時防止SET 和 SEU。然而，BISER 導致更多的面積和而這些面積會增加軟性電子錯誤率。因此，我們提出的可防護軟性電子錯誤設計閘（SERL），有比較小的面積且有更好的SER 保護效果。結合其他常規閘，SERL 可以使用的相同的延遲時間，消除比BISER 還要多的軟性電子錯誤。實驗結果表明，SERL 在設備和系統上比BISER 減少20％的SER，SERL 同時也比BISER 減少了7％的面積。因此，SERL 是一種有效的設計，消除在時序電路的SERs 同時又只運用一點小的面積。

As transistor size continues to shrink, VLSI circuits become more and more susceptible to the soft errors induced by adiation particle strike. Soft error occurs when a transient pulse propagates to a memory cell and gets latched to incur a single event transient (SET) or to flip the value stored in memory cell, to incur a single event upset (SEU). Soft errors can cause system failure and unpredictable erroneous condition. In order to eliminate soft errors, previous researches have proposed different DFF rchitectures for SER protection. One of the state-of-the-art designs is BISER, which protects designs against SET and SEU, simultaneously. However, BISER adds more transistors to the original DFF resulting in more area overhead and higher probability of soft error. Therefore, we propose a soft error resilient latch (SERL) which has less area overhead and offers better SER protection. Combined with regular latches, SERL-DFF can use the same delay time to eliminate more soft errors than BISER does. Experimental results show that SERL-DFF has 20% more SER reduction than BISER at the device and system level and uses 7% less area than BISER. As a result, SERL-DFF is effective in eliminating SERs in sequential circuits and only has a small area overhead.