標題: | A 2 GOPS Quad-Mean Shift Processor with Early Termination for Machine Learning Applications |
作者: | Tsai, Chang-Hung Lee, Hui-Hsuan Yu, Wan-Ju Lee, Chen-Yi 電機工程學系 Department of Electrical and Computer Engineering |
公開日期: | 1-一月-2014 |
摘要: | This paper proposes a 2 GOPS quad-mean shift processor (Q-MSP) architecture for data clustering and machine learning applications. By exploiting the linear approximation approach and early termination mechanism, the proposed algorithm can reduce 70% and 40% computational complexity, respectively. Moreover, 4 mean shift processor cores are integrated into the proposed architecture to support parallel processing to further improve system performance. Implemented in Xilinx Virtex-7 FPGA, this architecture occupies 65k LUTs and 3.3MB block memory to achieve 2 GOPS throughput operated at 125MHz. |
URI: | http://hdl.handle.net/11536/124892 |
ISBN: | 978-1-4799-3432-4 |
ISSN: | 0271-4302 |
期刊: | 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 157 |
結束頁: | 160 |
顯示於類別: | 會議論文 |