完整後設資料紀錄
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dc.contributor.authorSu, Ping-Hsunen_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2015-07-21T08:31:14Z-
dc.date.available2015-07-21T08:31:14Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-5433-9en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/124932-
dc.description.abstractDesign rule is an important interface between design and manufacturing. It becomes more complex as the process advances to 16-nm and beyond. Current approaches to generate design rules are empirical shrink and lithographic simulation. However, it is time-consuming and costly to revise design rules for performance boost and yield improvement after design rules are frozen. Early performance gains in early design rule development without cost increase and yield loss will benefit semiconductor industry. In this work, we for the first time consider 16-nm bulk FinFET standard cell performance, yield, area, and layout style simultaneously to optimize design rules to meet ITRS by using geometric programming. Optical proximity correction, and electromagnetic field and circuit simulations are performed for objective function evaluation. The result achieves more than 100%-delay and 50%-yield improvement without area change by this systematic and statistical approach.en_US
dc.language.isoen_USen_US
dc.subjectdesign ruleen_US
dc.subjectareaen_US
dc.subjectpoweren_US
dc.subjectperformanceen_US
dc.subjectvariabilityen_US
dc.subjectstandard cellen_US
dc.subjectoptimizationen_US
dc.subjectgeometry programmingen_US
dc.subjectbulk FinFETen_US
dc.titleDesign Optimization of 16-nm Bulk FinFET Technology via Geometric Programmingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL WORKSHOP ON COMPUTATIONAL ELECTRONICS (IWCE)en_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.identifier.wosnumberWOS:000345736700071en_US
dc.citation.woscount0en_US
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