A VLSI Implementation of Variation-Free PUF-based Processor for RFID Applications

Abstract

The Physically Unclonable Function (PUF) has been presented to defend physical attacks for RFID authentication. The silicon PUF employs difference of gate and wire delays on silicon chip to protect hardware copies of RFID. Because of the process variation in IC manufacturing, each silicon chip has different delays for gates and wires and, thus, the PUF-based encryption on each chip has different output even though the logic design is the same as the others. Research has been focusing on low-cost PUF implementation with a chain of logic blocks. However, some operating variations such as power-supply voltage and temperature variations might cause the failure of authentication. This paper presents a variation-free PUF-based processor with error control coding (ECC) technology. We used the ECC encoder to generate parity code for variation compensation. Therefore, our chip can generate a variation-free PUF encryption for RFID application. The chip is implemented by TSMC 0.18um CMOS process. As shown in the results, the chip area is as small as 0.83 mm<^>2 and its power dissipation is 87 uW.