標題: | An Efficient ASIC Implementation of 16-channel On-line Recursive ICA Processor for Real-time EEG System |
作者: | Fang, Wai-Chi Huang, Kuan-Ju Chou, Chia-Ching Chang, Jui-Chung Cauwenberghs, Gert Jung, Tzyy-Ping 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-一月-2014 |
摘要: | This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency. |
URI: | http://hdl.handle.net/11536/125043 |
ISBN: | 978-1-4244-7929-0 |
ISSN: | 1557-170X |
期刊: | 2014 36TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC) |
起始頁: | 3849 |
結束頁: | 3852 |
顯示於類別: | 會議論文 |