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dc.contributor.authorKu, Jerry C. Y.en_US
dc.contributor.authorHuang, Ryan H. -M.en_US
dc.contributor.authorLin, Louis Y. -Z.en_US
dc.contributor.authorWen, Charles H. -P.en_US
dc.date.accessioned2015-07-21T08:30:53Z-
dc.date.available2015-07-21T08:30:53Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-2816-3en_US
dc.identifier.issn2153-6961en_US
dc.identifier.urihttp://hdl.handle.net/11536/125049-
dc.description.abstractMulti-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption (CI), (2) ripple compaction (RC) and (3) fan-in-cone based fault ordering (FIC) to deal with such problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fan-in-cone based fault ordering strategically arranges the fault list to reduce the number of test generations and thus speeds up the ATPG process. According to our experiments, the proposed parallel ATPG system effectively reduces 11% pattern count and achieves similar to 0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits.en_US
dc.language.isoen_USen_US
dc.titleSuppressing Test Inflation in Shared-Memory Parallel Automatic Test Pattern Generationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)en_US
dc.citation.spage664en_US
dc.citation.epage669en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000350791700118en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper