一個10 Gbps,高動態範圍之CMOS光通訊接收機

Abstract

本論文提出一個使用聯電(UMC)四十奈米CMOS製程實現之光通訊接收機。其具備每秒一百億位元(10Gb/s)的資料傳輸速度及15 dB之接收信號動態範圍， 且具備低功率消耗之優點，為現有文獻及技術報告中最佳者。 本晶片中整合了一個前端的轉阻放大器(Transimpedance Amplifier, TIA)、後級限幅放大器(Post-limiting amplifier)及自動增益控制(Auto gain control, AGC)電路。典型之轉阻放大器採用並聯回授式架構，其在接收端輸入大光電流的條件下，將造成輸出信號之飽和失真。此一問題雖可藉由降低回授電阻值來解決，然而其往往造成系統之開迴路主極點上升，導致相位邊限之劣化並產生穩定度之問題。 為克服上述困難，本設計利用自動增益控制器動態調整轉阻放大器之回授電阻值及核心電壓放大器之增益，使接收機前級電路在不同增益模態下達到穩定之開迴路增益及相位邊限，進而達到寬動態範圍操作並提升系統之穩定度。 本電路操作於 1.2伏特電壓之下，資料傳輸之能源效益達到 3.6 pJ/bit。在誤碼率(BER)皆小於〖10〗^(-12) 之條件下，接收機之靈敏度達到 -15 dBm。 晶片面積為0.334平方毫米。

This thesis describes the design of a 10 Gbps, 15 dB dynamic range optical receiver in UMC 40 nm CMOS process. It also has the advantage of low power consumption, and has the best performance in terms of dynamic range at 10 Gbps operation. The optical receiver consists of a transimpedance amplifier, a post limiting amplifier and an automatic gain controlled circuit. Typically, a shunt-shunt feedback amplifier is utilized in transimpedance amplifier (TIA) design. However, under the circumstance of large input photo current, it may result in output signal distortion. Although this problem can be circumvented by reducing the feedback resistor of TIA, it may induce a higher open loop dominant pole of TIA. Thus the phase margin will be degraded and may cause stability issue. To overcome the aforementioned problem, an automatic gain controlled circuit which dynamically adjusts the feedback resistor and voltage gain of TIA core amplifier is adopted in this design. It stabilizes the open loop gain of TIA and phase margin, so as to improve system stability under wide dynamic range operation. The experimental prototype is operated under 1.2 V supply, and achieves an energy efficiency of 3.6 pJ/bit. For bit error rate of less than 10-12, the input sensitivity is -15 dB. Chip size is 0.334 mm2.