標題: 應用於太陽能再生能源具廣負載範圍之多模式數位降壓器
A wide load range multi-mode digital buck converter for photovoltaic energy harvesting
作者: 林凱鈞
Lin, Kai-Chun
陳柏宏
Chen, Po-Hung
電子工程學系 電子研究所
關鍵字: 數位降壓器;太陽能再生能源;零電流偵測;digital buck converter;photovoltaic energy harvesting;zero current detection
公開日期: 2015
摘要: 近年來,隨著穿戴式產品的商品化,電池以外的能源獵取技術已成為延長電池使用時間的重要發展。其中,可永續利用且低汙染的再生能源近年來受到各方矚目,相關研究也逐漸受到重視。而在眾多再生能源之中,太陽發電的單位面積能提供較高的能量,所以具有發展無電池系統的高度潛力。其可應用的範圍包括無線感測器、物聯網以及生醫電子元件,在這些應用中,為了有效利用有限的太陽能,後端數位電路已廣泛運用低電壓低功耗技術,將電晶體操作於次臨界區。因此,發展低電壓且高效率的電源管理系統已成為目前的趨勢,藉此將太陽能發電所產生的不穩定電壓轉換為穩定的系統電壓。   本論文實現一個應用於太陽能再生能源之三模數位降壓器,最高轉換效率達92%,其輸入電壓設計在太陽能最大功率點0.55~0.65伏,而輸出電壓為0.35~0.5伏數位電路於次臨界導通區域下操作,有效的使用有限的太陽能再生能源。藉由結合脈波調變模式、頻率調變模式以及非同步模式,使三模數位降壓器涵蓋從50奈瓦到10毫瓦之負載範圍且從400奈瓦到10毫瓦有70%以上的效率,除此之外,藉由所提出之自應式零電流偵測用來追蹤下橋功率電晶體開關時間,使用數位機制來減少功率損耗;與類比方式相比,此數位零電流偵測有較低的操作電壓且有較小的功率消耗,藉此提高系統輕載時轉換效率,而非同步模式則將操作範圍延伸至50奈瓦。
Photovoltaic energy harvesting is an attractive method of developing battery-free systems, such as wireless sensors, biomedical electronics, and the internet of things (IoT). To sustain normal operation with a limited power budget, low-power digital circuits operating in the near/sub-threshold region are widely used in such applications. Therefore, the design of a low-voltage buck converter which converts the harvested energy to the regulated output is dispensable. In this work, a tri-mode digital buck converter for photovoltaic energy harvesting with a maximum conversion efficiency of 92% is proposed. The input voltage (VIN) is targeted to 0.55−0.65V so as to meet the maximum power point voltages of the photovoltaic cell. The output voltage (VOUT) ranges from 0.35−0.5V, so that near/sub-threshold CMOS digital circuits utilize photovoltaic energy effectively. By integrating pulse-width modulation (PWM), pulse-frequency modulation (PFM), and asynchronous mode (AM), together with digital self-tracking zero current detection (ST-ZCD), the tri-mode digital buck converter provides wide output range from 50nW to 10mW, while achieving more than 70% efficiency from 400nW to 10mW. In addition, the proposed digital ST-ZCD automatically tracks the off-time of the power transistor, thus reducing the PFM power budget. Compared with the analog approach, the digital method is more robust under low voltage operation and the quiescent current can be reduced in order to improve the efficiency under low-power applications.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070150282
http://hdl.handle.net/11536/125568
Appears in Collections:Thesis