應用於人工電子耳使用新穎資料加權平均法之三角積分類比數位轉換器

Abstract

近年來生醫電子系統蓬勃發展，低功耗、低雜訊正是生醫電子重要的研究方向。其中類比數位轉換器在生醫電子系統中扮演重要角色。本篇論文即是設計一個應用於人工電子耳系統的三角積分類比數位轉換器。對一個多位元的三角積分類比數位轉換器而言，在回授的數位類比轉換器中通常會加入資料加權平均演算法來抑制因元件的不匹配所造成的諧波失真。但傳統的資料加權平均法會在基頻內產生突波，原因為指標重複地和周期性地選擇類比數位轉換器的單位電流源。本論文提出新穎的資料加權平均法來來降低突波。這方法是利用在指標中隨機選擇加0或1。基頻的突波下降，SFDR和SNDR也提升了許多。 本篇論文量測結果顯示最大訊號失真雜訊比為50.1dB，動態範圍為58dB，本次晶片以台積電0.18微米1P6M混和訊號互補式金氧半導體製程所製造，晶片面積為1.168 x 0.632 mm2，在1.8V的供應電壓下消耗功率約為452 µW。

In recent years, with the rapid of development of biomedical electronic systems, low power consumption and low noise have become very important research topic. The ADC plays a very important role in biomedical electronic systems. In this thesis, the design of the delta-sigma A/D converter for applications of cochlear prosthesis has been implemented. A multi-bit delta-sigma ADC uses data weighted averaging (DWA) algorithm applied to the feedback DAC. DWA algorithm has been used to suppress the harmonic distortions. The pointer selection of DAC elements is used cyclically, which has resulted in some baseband tones. A novel DWA algorithm is proposed to further reduce baseband tones than the conventional DWA. The method randomly adds 0 or 1 during the pointer selection, which has improved the performance of SFDR and SNDR. In this thesis, the measurement results show that the peak signal to noise and distortion ratio is 50.1dB and the dynamic range is 58dB. The chip was fabricated by TSMC 0.18µm 1P6M CMOS mixed signal process. The chip area is 1.168 x 0.632 mm2 and power consumption is 452µW from a 1.8-V power supply.