應用於人工電子耳之低功率連續時間三角積分類比數位轉換器

Abstract

本篇論文中，我們將以台積電180奈米製程製作設計適用於人工電子耳系統的連續時間類比數位轉換器，當中包含一個三階連續時間三角積分調變器，取樣頻率為1.536MHz，訊號寬24KHz，OSR為32。為進一步降低功號，使用四位元單調切換式SAR量化器取代一般的Flash量化器。緊接在三角積分調變器後加上了三級架構的降頻濾波器，把樣本輸出頻率從1.536MHz降回音頻Nyquist Rate的48KHz。文中將顯示這個系統的模擬結果與佈局圖。 第一版晶片量測結果在輸入訊號19.5KHz時最大訊號雜訊比SNR=78.2dB，75 dB動態範圍，供應電壓1.8v下消耗功率為410uW，晶片面積為0.539mm2。第二版晶片中三角積分調變器晶片面積為0.634 mm2，在1.8v的供應電壓下消耗功率約為208uW。而三級降頻濾波器面積為0.63 mm2 ，消耗功率為43.8uW，由post layout simulation的結果，可得知96.4dB的訊號雜訊與失真比。

In this thesis, the design of the A/D converters for applications of the cochlear prosthesis system will be introduced, which were fabricated in TSMC 0.18-m CMOS process. The system includes a third-order continuous-time sigma-delta modulator and a three-stage decimation filter. The sampling rate is set to 1.536 MHz with 24 kHz signal bandwidth and the OSR of 32. A four-bit monotonous switching SAR quantizer is also used in the system. Both simulation results and layout will be presented. Results of the first chip show that for a 19.5KHz input signal, the ADC achieves a dynamic range of 75dB and a peak signal-to-noise ratio of 78.2dB, and dissipates 410uW from a 1.8-V power supply with a 0.539 mm2 active area. Post-layout simulation of the second-version chip shows that it achieves a peak signal-to-noise -distortion ratio of 96.4 dB and dissipates about 208uW from 1.8V supply voltage. The active area of the Sigma-Delta modulator is 0.634 mm2. The area of the three-stage decimation filter is 0.63 mm2 with the power consumption of 43.8uW.