應用於助聽器之低電壓低功率三角積分調變器

Abstract

近年來由於積體電路製程的進步，每個電晶體的尺寸亦隨之降低，使得在晶片內電路的密度可以愈做愈高。然而，電晶體的臨界電壓並沒有隨著製程的進步而線性的降低．這將會增加電路設計上的困難，尤其是在深次微米的製程上。因此，低電壓的電路設計顯得格外重要，亦是未來發展的一大趨勢。 在此論文中，提出一個應用於助聽器之低功率與低電壓的三角積分調變器。使用反相器(Inverter)做為電容切換式積分器中的運算放大器，用以實現一個三階的三角積分調變器。為了降低製程偏移的影響，使用一些電路技巧，用以消除運算放大器的偏移電壓。由於低電壓的系統設計，會使得切換的開關無法正常的導通或關閉，因此，一般低電壓的電路設計亦會在此介紹。除此之外，因為低電壓系統對於雜訊的影響較大，所以亦會在所提出的電路架構中做完整的推導。另外，時脈對開關所造成的雜訊，可以藉由多餘的開關(dummy switches)製造反相的雜訊以消除單一開關所產生之雜訊。 所提出的電路架構將被實現在TSMC CMOS 0.18 m的製程，其晶片面積為 (不包含PAD)，當取樣頻率在2M Hz、頻寬被設定在20kHz及電壓為1V時，可以得到最大之訊號失真雜訊比(SNDR)為69.01dB，訊號雜訊比(SNR)為75.74dB，動態範圍(Dynamic Range)為76dB。

In recent years, the dimension scales down with the advance of IC fabrication technology such that the circuit component density is becoming higher and higher. However, the threshold voltage is not scaled down linearly with the dimension. It increases the difficulty of circuit design, especially with the deep sub-micron process. Therefore, the low voltage circuit design is a necessary trend for the future. The design of a low-voltage and low-power sigma-delta modulator is presented for hearing aids application. A third-order single-loop topology is implemented using switched-capacitor circuits with inverter opamp. To decrease process variation in inverter opamp, the technique of offset cancellation is introduced. Due to low voltage system, the switches driving problem and noise issue are also discussed. The clock feed-through noise is reduced using dummy switches. The proposed sigma-delta modulator is implemented using TSMC CMOS 0.18 m process with active die area of . The peak SNDR is 69.01dB, SNR is 75.74dB, and DR is 76.61dB at a sampling rate of 2M Hz and signal bandwidth of 20k Hz under single 1.0V supply voltage.