標題: 低功率數位自動增益控制及積分三角調變器
Low Power Digital AGC and Sigma-Delta Modulator for Audio Front-End Circuit
作者: 王村鑫
Tsun-Hsin Wang
蘇朝琴
ChauChin Su
電控工程研究所
關鍵字: 三角積分調變器;低電壓;低功率;自動增益控制器;可變增益放大器;數位類比轉換器;sigma-delta modulator;low-voltage;low-power;automatic gain control;variable gain amplifier;digital to analog converter
公開日期: 2007
摘要: 近年來積體電路製程進步,晶片在單位面積裡面可放進更多電晶體.,使得晶片的應用越來越廣泛.應用在音頻方面的電池裝置產品中,例如助聽器、聽診器...等等,希望所使用的晶片擁有低電壓、低面積、低功率,在這篇論文裡,實現一個應用於音頻前端電路的低電壓、低面積、低功率的數位自動控制器和積分三角調變器。 採用積分三角調變器輸出端直接迴授方式去設計一個數位自動控制器,沒有經過後級抽樣濾波器,進而可以達到節省面積、降低功率和減少自動增益控制器迴路延遲。為了降低三角積分調變器的功率消耗,使用反向器轉導運算放大器和一個全動態式比較器。為了整流積分三角調變器的輸出位元流,在此也提出了一個位元流整流器。數位類比轉換器方面,提出一個低面積循環式數位類比轉換器。 所提出的電路架構將被實現在TSMC CMOS 0.18 m的製程,其晶片面積為0.347um*0.429um(不包含PAD),設計在音頻頻寬250Hz~10kHz,操作電壓1V,擁有12Bit的解析度,動態範圍87dB。此電路系統總共的功率消耗為 42.3 uW
IC processing technologies have a great improvement recently. There are more transistors per unit area. Therefore, applications are more and more extensive. Battery device products for audio applications, such as hearing aids, stethoscope, etc, hope circuits to operate at 1ow voltage, low area, and low power. In this thesis, a low-voltage low-area low-power digital automatic gain control (AGC) with a sigma-delta modulator for audio front-end circuit is realized. This thesis utilizes a direct feedback at the sigma-delta modulator output to design the digital AGC. It does not go through a decimation filter. Thus it decreases the area, power consumption, and latency of the AGC loop. To decrease the power consumption of the modulator, inverter operational transconductance amplifiers (OTA) are used and a pure dynamic comparator is designed. To rectifier a bit stream of the modulator output, a bit-stream rectifier is presented. In terms of digital to analog converter, a low area recurring DAC is presented. The proposed circuit is designed in TSMC 1P6M 0.18 m CMOS process. Its active die area is 0.347um*0.429um. The signal bandwidth is designed in an audio bandwidth from 250Hz to 10 kHz, and the resolution is 12bit. The dynamic range(DR) is 87dB. The supply voltage is 1.0V. The total power consumption of the proposed circuit is 42.3 μW.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009412586
http://hdl.handle.net/11536/80720
顯示於類別:畢業論文


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