60GHz室內無線Gb/s SC/OFDM基頻接收器的FPGA 雛型設計

Abstract

在數位IC實現流程中，FPGA原型設計是非常重要的一步。在IC設計與下線製造之前必須先驗證功能的正確性。 FPGA提供一個方便且快捷的方式來驗證硬體設計。本文提出了IEEE 802.15.3c及802.11ad標準的雙模無線基頻接收機。它具有單載波（SC）和高速接口（HSI）兩種操作模式。在單載波模式中基頻接收機使用單載波來傳送數據，而高速接口模式是基於正交分頻多工(OFDM) 來傳送數據。在接收機中，共有同步，頻域等化器和相位雜訊消除三個主要區塊。SC和HSI模式共享所有區塊以降低整體硬體複雜度和功率消耗。此外，此論文不僅完成數位基頻之FPGA原型設計，也討論用不同的方法來將ASIC特定的RTL設計用於FPGA實現，同時亦提出各種方法來提升系統的操作頻率（速度）使得基頻接收機可以在FPGA上達到Gb/s的數據傳輸速度。整個基頻內接收機在Xilinx FPGA VC707上實現並且驗證其功能性。在驗證方面，基頻接收機的輸出使用ChipScopeTM Pro 內建邏輯分析儀進行分析與偵錯。基頻接收機的操作頻率工作在95MHz並使用8X-並行架構。在HSI模式下的數據傳輸速率分別可以達到1.5 Gb/s (QPSK)和4.5 Gb/s (64 QAM)。

In practical Digital IC implementation flow, FPGA prototyping is a very important step. Before the hardware design is signed-off for tape-out, it is essential to verify the functional correctness and performance of the IC/hardware in constrained test environment. FPGAs provide an easy and fast way to verify the hardware design. This thesis proposes a dual mode (SC and HSI) and dual standard wireless baseband receiver which implements the IEEE standards 802.15.3c and 802.11.ad. It has two operation modes, single carrier (SC) and high speed interface (HSI). The single carrier mode receives data on a single carrier while the high speed interface mode is based on orthogonal frequency division multiplexing, OFDM. There are three main blocks of the receiver, the synchronization block, frequency domain equalizer, and phase noise cancellation. All the blocks share the hardware of the SC and HSI modes to reduce the area, complexity and power consumption. Besides, this thesis discusses not only the FPGA prototyping flow with different methods to translate an ASIC specific RTL design for FPGA implementation but also various methods to upgrade the operation frequency (speed) of the system to achieve target Gb/s speeds on FPGA. The baseband receiver is implemented on Xilinx VC707 FPGA evaluation board and the receiver works at 95MHz with 8X-parallelism architecture. The output from the baseband receiver is analyzed using ChipscopeTM Pro integrated logic analyzer. The data rates achieved from the prototype are 1.5 Gb/s and 4.5 Gb/s for QPSK and 64QAM data in HSI mode, respectively.